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Message-ID: <202309230103.YgvYkSCn-lkp@intel.com>
Date: Sat, 23 Sep 2023 01:43:25 +0800
From: kernel test robot <lkp@...el.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>,
Lizhi Hou <lizhi.hou@....com>, Brian Xu <brian.xu@....com>,
Raj Kumar Rampelli <raj.kumar.rampelli@....com>,
Vinod Koul <vkoul@...nel.org>, Michal Simek <monstr@...str.eu>
Cc: oe-kbuild-all@...ts.linux.dev, dmaengine@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
linux-kernel@...r.kernel.org,
Miquel Raynal <miquel.raynal@...tlin.com>
Subject: Re: [PATCH v2 2/2] dmaengine: xilinx: xdma: Support cyclic transfers
Hi Miquel,
kernel test robot noticed the following build warnings:
[auto build test WARNING on v6.6-rc2]
[also build test WARNING on linus/master next-20230921]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Miquel-Raynal/dmaengine-xilinx-xdma-Prepare-the-introduction-of-cyclic-transfers/20230923-002252
base: v6.6-rc2
patch link: https://lore.kernel.org/r/20230922162056.594933-3-miquel.raynal%40bootlin.com
patch subject: [PATCH v2 2/2] dmaengine: xilinx: xdma: Support cyclic transfers
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20230923/202309230103.YgvYkSCn-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230923/202309230103.YgvYkSCn-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309230103.YgvYkSCn-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/dma/xilinx/xdma.c:262: warning: Function parameter or member 'cyclic' not described in 'xdma_alloc_desc'
vim +262 drivers/dma/xilinx/xdma.c
17ce252266c7f0 Lizhi Hou 2023-01-19 254
17ce252266c7f0 Lizhi Hou 2023-01-19 255 /**
17ce252266c7f0 Lizhi Hou 2023-01-19 256 * xdma_alloc_desc - Allocate descriptor
17ce252266c7f0 Lizhi Hou 2023-01-19 257 * @chan: DMA channel pointer
17ce252266c7f0 Lizhi Hou 2023-01-19 258 * @desc_num: Number of hardware descriptors
17ce252266c7f0 Lizhi Hou 2023-01-19 259 */
17ce252266c7f0 Lizhi Hou 2023-01-19 260 static struct xdma_desc *
9dfa9406316d5c Miquel Raynal 2023-09-22 261 xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num, bool cyclic)
17ce252266c7f0 Lizhi Hou 2023-01-19 @262 {
17ce252266c7f0 Lizhi Hou 2023-01-19 263 struct xdma_desc *sw_desc;
17ce252266c7f0 Lizhi Hou 2023-01-19 264 struct xdma_hw_desc *desc;
17ce252266c7f0 Lizhi Hou 2023-01-19 265 dma_addr_t dma_addr;
17ce252266c7f0 Lizhi Hou 2023-01-19 266 u32 dblk_num;
34df67fe3afc84 Miquel Raynal 2023-09-22 267 u32 control;
17ce252266c7f0 Lizhi Hou 2023-01-19 268 void *addr;
17ce252266c7f0 Lizhi Hou 2023-01-19 269 int i, j;
17ce252266c7f0 Lizhi Hou 2023-01-19 270
17ce252266c7f0 Lizhi Hou 2023-01-19 271 sw_desc = kzalloc(sizeof(*sw_desc), GFP_NOWAIT);
17ce252266c7f0 Lizhi Hou 2023-01-19 272 if (!sw_desc)
17ce252266c7f0 Lizhi Hou 2023-01-19 273 return NULL;
17ce252266c7f0 Lizhi Hou 2023-01-19 274
17ce252266c7f0 Lizhi Hou 2023-01-19 275 sw_desc->chan = chan;
17ce252266c7f0 Lizhi Hou 2023-01-19 276 sw_desc->desc_num = desc_num;
9dfa9406316d5c Miquel Raynal 2023-09-22 277 sw_desc->cyclic = cyclic;
17ce252266c7f0 Lizhi Hou 2023-01-19 278 dblk_num = DIV_ROUND_UP(desc_num, XDMA_DESC_ADJACENT);
17ce252266c7f0 Lizhi Hou 2023-01-19 279 sw_desc->desc_blocks = kcalloc(dblk_num, sizeof(*sw_desc->desc_blocks),
17ce252266c7f0 Lizhi Hou 2023-01-19 280 GFP_NOWAIT);
17ce252266c7f0 Lizhi Hou 2023-01-19 281 if (!sw_desc->desc_blocks)
17ce252266c7f0 Lizhi Hou 2023-01-19 282 goto failed;
17ce252266c7f0 Lizhi Hou 2023-01-19 283
9dfa9406316d5c Miquel Raynal 2023-09-22 284 if (cyclic)
9dfa9406316d5c Miquel Raynal 2023-09-22 285 control = XDMA_DESC_CONTROL_CYCLIC;
9dfa9406316d5c Miquel Raynal 2023-09-22 286 else
34df67fe3afc84 Miquel Raynal 2023-09-22 287 control = XDMA_DESC_CONTROL(1, 0);
34df67fe3afc84 Miquel Raynal 2023-09-22 288
17ce252266c7f0 Lizhi Hou 2023-01-19 289 sw_desc->dblk_num = dblk_num;
17ce252266c7f0 Lizhi Hou 2023-01-19 290 for (i = 0; i < sw_desc->dblk_num; i++) {
17ce252266c7f0 Lizhi Hou 2023-01-19 291 addr = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &dma_addr);
17ce252266c7f0 Lizhi Hou 2023-01-19 292 if (!addr)
17ce252266c7f0 Lizhi Hou 2023-01-19 293 goto failed;
17ce252266c7f0 Lizhi Hou 2023-01-19 294
17ce252266c7f0 Lizhi Hou 2023-01-19 295 sw_desc->desc_blocks[i].virt_addr = addr;
17ce252266c7f0 Lizhi Hou 2023-01-19 296 sw_desc->desc_blocks[i].dma_addr = dma_addr;
17ce252266c7f0 Lizhi Hou 2023-01-19 297 for (j = 0, desc = addr; j < XDMA_DESC_ADJACENT; j++)
34df67fe3afc84 Miquel Raynal 2023-09-22 298 desc[j].control = cpu_to_le32(control);
17ce252266c7f0 Lizhi Hou 2023-01-19 299 }
17ce252266c7f0 Lizhi Hou 2023-01-19 300
9dfa9406316d5c Miquel Raynal 2023-09-22 301 if (cyclic)
9dfa9406316d5c Miquel Raynal 2023-09-22 302 xdma_link_cyclic_desc_blocks(sw_desc);
9dfa9406316d5c Miquel Raynal 2023-09-22 303 else
34df67fe3afc84 Miquel Raynal 2023-09-22 304 xdma_link_sg_desc_blocks(sw_desc);
17ce252266c7f0 Lizhi Hou 2023-01-19 305
17ce252266c7f0 Lizhi Hou 2023-01-19 306 return sw_desc;
17ce252266c7f0 Lizhi Hou 2023-01-19 307
17ce252266c7f0 Lizhi Hou 2023-01-19 308 failed:
17ce252266c7f0 Lizhi Hou 2023-01-19 309 xdma_free_desc(&sw_desc->vdesc);
17ce252266c7f0 Lizhi Hou 2023-01-19 310 return NULL;
17ce252266c7f0 Lizhi Hou 2023-01-19 311 }
17ce252266c7f0 Lizhi Hou 2023-01-19 312
--
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