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Message-Id: <20230922085701.3164-2-yongxuan.wang@sifive.com>
Date: Fri, 22 Sep 2023 08:56:47 +0000
From: Yong-Xuan Wang <yongxuan.wang@...ive.com>
To: linux-riscv@...ts.infradead.org, kvm-riscv@...ts.infradead.org
Cc: greentime.hu@...ive.com, vincent.chen@...ive.com, tjytimi@....com,
alex@...ti.fr, Yong-Xuan Wang <yongxuan.wang@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <apatel@...tanamicro.com>,
Guo Ren <guoren@...nel.org>,
Andrew Jones <ajones@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
wchen <waylingii@...il.com>, Heiko Stuebner <heiko@...ech.de>,
Jisheng Zhang <jszhang@...nel.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Alexandre Ghiti <alexghiti@...osinc.com>,
Kemeng Shi <shikemeng@...weicloud.com>,
"Matthew Wilcox (Oracle)" <willy@...radead.org>,
Charlie Jenkins <charlie@...osinc.com>,
Sergey Matyukevich <sergey.matyukevich@...tacore.com>,
David Hildenbrand <david@...hat.com>,
Qinglin Pan <panqinglin2020@...as.ac.cn>,
Rick Edgecombe <rick.p.edgecombe@...el.com>,
Sunil V L <sunilvl@...tanamicro.com>,
Evan Green <evan@...osinc.com>, linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/3] RISC-V: Detect and Enable Svadu Extension Support
We detect Svadu extension support from DTB and add arch_has_hw_pte_young()
to enable optimization in MGLRU and __wp_page_copy_user() if Svadu
extension is available.
Co-developed-by: Jinyu Tang <tjytimi@....com>
Signed-off-by: Jinyu Tang <tjytimi@....com>
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@...ive.com>
---
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/pgtable.h | 6 ++++++
arch/riscv/kernel/cpufeature.c | 1 +
4 files changed, 9 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 777cb8299551..10648b372a2a 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -194,6 +194,7 @@
/* xENVCFG flags */
#define ENVCFG_STCE (_AC(1, ULL) << 63)
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
+#define ENVCFG_HADE (_AC(1, ULL) << 61)
#define ENVCFG_CBZE (_AC(1, UL) << 7)
#define ENVCFG_CBCFE (_AC(1, UL) << 6)
#define ENVCFG_CBIE_SHIFT 4
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b7b58258f6c7..1013661d6516 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -58,6 +58,7 @@
#define RISCV_ISA_EXT_ZICSR 40
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
+#define RISCV_ISA_EXT_SVADU 43
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index b2ba3f79cfe9..028b700cd27b 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -629,6 +629,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
+#define arch_has_hw_pte_young arch_has_hw_pte_young
+static inline bool arch_has_hw_pte_young(void)
+{
+ return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
+}
+
/*
* THP functions
*/
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1cfbba65d11a..ead378c04991 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -178,6 +178,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+ __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
--
2.17.1
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