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Message-ID: <20230922-bagel-hyphen-aae5b1b88b21@spud>
Date: Fri, 22 Sep 2023 10:28:04 +0100
From: Conor Dooley <conor@...nel.org>
To: Yong-Xuan Wang <yongxuan.wang@...ive.com>
Cc: linux-riscv@...ts.infradead.org, kvm-riscv@...ts.infradead.org,
greentime.hu@...ive.com, vincent.chen@...ive.com, tjytimi@....com,
alex@...ti.fr, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Svadu Entry
On Fri, Sep 22, 2023 at 08:56:48AM +0000, Yong-Xuan Wang wrote:
> Add an entry for the Svadu extension to the riscv,isa-extensions property.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@...ive.com>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..b5a0aed0165b 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -147,6 +147,12 @@ properties:
> ratified at commit 3f9ed34 ("Add ability to manually trigger
> workflow. (#2)") of riscv-time-compare.
>
> + - const: svadu
> + description: |
> + The standard Svadu supervisor-level extension for hardware updating
> + of PTE A/D bits as frozen at commit b65e07c ("move to Frozen
> + state") of riscv-svadu.
> +
> - const: svinval
> description:
> The standard Svinval supervisor-level extension for fine-grained
> --
> 2.17.1
>
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