linux-kernel - Re: [PATCH v2 08/11] serial: 8250

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Message-ID: <CAHAQgRCiAvvowhv095cm5X4aDUhJSr7j92a84KJto40Cj4wd-w@mail.gmail.com>
Date:   Fri, 22 Sep 2023 19:39:00 +0800
From:   Chen Wang <unicornxw@...il.com>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc:     Ben Dooks <ben.dooks@...ethink.co.uk>, aou@...s.berkeley.edu,
        chao.wei@...hgo.com, conor@...nel.org, devicetree@...r.kernel.org,
        guoren@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, robh+dt@...nel.org,
        xiaoguang.xing@...hgo.com, Chen Wang <wangchen20@...as.ac.cn>
Subject: Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support

Regards,

unicornx

Emil Renner Berthing <emil.renner.berthing@...onical.com> 于2023年9月22日周五 18:40写道：
>
> Ben Dooks wrote:
> > On 20/09/2023 07:40, Chen Wang wrote:
> > > From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> > >
> > > Add quirk to skip setting the input clock rate for the uarts on the
> > > Sophgo SG2042 SoC similar to the StarFive JH7100.
> >
> > I'd love an actual explanation of why this is necessary here.
>
> Makes sense. For the JH7100 the commit message is:
>
>   On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
>   exactly 16 * 115200Hz and many other common bitrates. Trying this will
>   only result in a higher input clock, but low enough that the UART's
>   internal divisor can't come close enough to the baud rate target.
>   So rather than try to set the input clock it's better to skip the
>   clk_set_rate call and rely solely on the UART's internal divisor.
>
> @Chen Wang is this also true for the SG2042?
>
> /Emil

Emil & Ben,
I need to double-confirm this with sophgo engineers. Because they are
off work now, I will probably get back to you later next week.