linux-kernel - Re: [PATCH 2/3] arm64: dts: qcom: Add USB3 and PHY support

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Message-ID: <29b774d4-3759-4b49-926e-551c92d3f8c7@linaro.org>
Date:   Sat, 23 Sep 2023 22:19:18 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Rohit Agarwal <quic_rohiagar@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: Add USB3 and PHY support

On 22/09/2023 14:50, Rohit Agarwal wrote:
> Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
> HS PHY on SDX75.

Please fix the subject to mention the platform.

Other than that, LGTM.

> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 116 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 116 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index dd3a525..c44cdd1 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -473,6 +473,47 @@
>   			};
>   		};
>   
> +		usb_hsphy: phy@...000 {
> +			compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
> +			reg = <0x0 0x00ff4000 0x0 0x154>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> +			clock-names = "ref";
> +
> +			resets = <&gcc GCC_QUSB2PHY_BCR>;
> +
> +			status = "disabled";
> +		};
> +
> +		usb_qmpphy: phy@...000 {
> +			compatible = "qcom,sdx75-qmp-usb3-uni-phy";
> +			reg = <0x0 0x00ff6000 0x0 0x2000>;
> +
> +			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
> +				 <&gcc GCC_USB2_CLKREF_EN>,
> +				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
> +			clock-names = "aux",
> +				      "ref",
> +				      "cfg_ahb",
> +				      "pipe";
> +
> +			power-domains = <&gcc GCC_USB3_PHY_GDSC>;
> +
> +			resets = <&gcc GCC_USB3_PHY_BCR>,
> +				 <&gcc GCC_USB3PHY_PHY_BCR>;
> +			reset-names = "phy",
> +				      "phy_phy";
> +
> +			#clock-cells = <0>;
> +			clock-output-names = "usb3_uni_phy_pipe_clk_src";
> +
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +		};
> +
>   		system_noc: interconnect@...0000 {
>   			compatible = "qcom,sdx75-system-noc";
>   			reg = <0x0 0x01640000 0x0 0x4b400>;
> @@ -493,6 +534,81 @@
>   			#hwlock-cells = <1>;
>   		};
>   
> +		usb: usb@...8800 {
> +			compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
> +			reg = <0x0 0x0a6f8800 0x0 0x400>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
> +				 <&gcc GCC_USB30_MASTER_CLK>,
> +				 <&gcc GCC_USB30_MSTR_AXI_CLK>,
> +				 <&gcc GCC_USB30_SLEEP_CLK>,
> +				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
> +			clock-names = "cfg_noc",
> +				      "core",
> +				      "iface",
> +				      "sleep",
> +				      "mock_utmi";
> +
> +			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
> +					  <&gcc GCC_USB30_MASTER_CLK>;
> +			assigned-clock-rates = <19200000>, <200000000>;
> +
> +			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&pdc 9 IRQ_TYPE_EDGE_RISING>,
> +					      <&pdc 10 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "hs_phy_irq",
> +					  "ss_phy_irq",
> +					  "dm_hs_phy_irq",
> +					  "dp_hs_phy_irq";
> +
> +			power-domains = <&gcc GCC_USB30_GDSC>;
> +
> +			resets = <&gcc GCC_USB30_BCR>;
> +
> +			interconnects = <&system_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
> +					<&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_USB3 0>;
> +			interconnect-names = "usb-ddr",
> +					     "apps-usb";
> +
> +			status = "disabled";
> +
> +			usb_dwc3: usb@...0000 {
> +				compatible = "snps,dwc3";
> +				reg = <0x0 0x0a600000 0x0 0xcd00>;
> +				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +				iommus = <&apps_smmu 0x80 0x0>;
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_enblslpm_quirk;
> +				phys = <&usb_hsphy>,
> +				       <&usb_qmpphy>;
> +				phy-names = "usb2-phy",
> +					    "usb3-phy";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						usb_1_dwc3_hs: endpoint {
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						usb_1_dwc3_ss: endpoint {
> +						};
> +					};
> +				};
> +			};
> +		};
> +
>   		pdc: interrupt-controller@...0000 {
>   			compatible = "qcom,sdx75-pdc", "qcom,pdc";
>   			reg = <0x0 0xb220000 0x0 0x30000>,

-- 
With best wishes
Dmitry