linux-kernel - [PATCH AUTOSEL 6.5 36/41] riscv: errata: fix T-Head dcache.cva encoding

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Message-Id: <20230924131529.1275335-36-sashal@kernel.org>
Date:   Sun, 24 Sep 2023 09:15:24 -0400
From:   Sasha Levin <sashal@...nel.org>
To:     linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc:     Icenowy Zheng <uwu@...nowy.me>,
        Sergey Matyukevich <sergey.matyukevich@...tacore.com>,
        Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>,
        Drew Fustini <dfustini@...libre.com>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Sasha Levin <sashal@...nel.org>, paul.walmsley@...ive.com,
        palmer@...belt.com, aou@...s.berkeley.edu,
        conor.dooley@...rochip.com, ajones@...tanamicro.com,
        samuel@...lland.org, prabhakar.mahadev-lad.rj@...renesas.com,
        jszhang@...nel.org, linux-riscv@...ts.infradead.org
Subject: [PATCH AUTOSEL 6.5 36/41] riscv: errata: fix T-Head dcache.cva encoding

From: Icenowy Zheng <uwu@...nowy.me>

[ Upstream commit 8eb8fe67e2c84324398f5983c41b4f831d0705b3 ]

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@...tacore.com>
Reviewed-by: Heiko Stuebner <heiko@...ech.de>
Reviewed-by: Guo Ren <guoren@...nel.org>
Tested-by: Drew Fustini <dfustini@...libre.com>
Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@...osinc.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/riscv/include/asm/errata_list.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8ce..feab334dd8329 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
 
-- 
2.40.1