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Message-Id: <20230924183103.49487-1-krzysztof.kozlowski@linaro.org>
Date: Sun, 24 Sep 2023 20:31:01 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Rohit Agarwal <quic_rohiagar@...cinc.com>,
Manivannan Sadhasivam <mani@...nel.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@...0000: phy-names:0: 'pciephy' was expected
Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP")
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index dd711484dfc9..c9790217320b 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -337,7 +337,7 @@ pcie_ep: pcie-ep@...0000 {
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_phy>;
- phy-names = "pcie-phy";
+ phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
--
2.34.1
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