linux-kernel - Re: [PATCH v2 0/9] KVM RISC-V Conditional Operations

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Message-ID: <20230925-gorged-boxer-3804735e2d18@spud>
Date:   Mon, 25 Sep 2023 16:33:15 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Anup Patel <apatel@...tanamicro.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        Atish Patra <atishp@...shpatra.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Shuah Khan <shuah@...nel.org>,
        Andrew Jones <ajones@...tanamicro.com>,
        Mayuresh Chitale <mchitale@...tanamicro.com>,
        devicetree@...r.kernel.org, kvm@...r.kernel.org,
        kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v2 0/9] KVM RISC-V Conditional Operations

On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> This series extends KVM RISC-V to allow Guest/VM discover and use
> conditional operations related ISA extensions (namely XVentanaCondOps
> and Zicond).
> 
> To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> branch at: https://github.com/avpatel/kvmtool.git
> 
> These patches are based upon the latest riscv_kvm_queue and can also be
> found in the riscv_kvm_condops_v2 branch at:
> https://github.com/avpatel/linux.git
> 
> Changes since v1:
>  - Rebased the series on riscv_kvm_queue
>  - Split PATCH1 and PATCH2 of v1 series into two patches
>  - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
>    of v1 series.
> 
> Anup Patel (9):
>   dt-bindings: riscv: Add XVentanaCondOps extension entry
>   RISC-V: Detect XVentanaCondOps from ISA string
>   dt-bindings: riscv: Add Zicond extension entry
>   RISC-V: Detect Zicond from ISA string

For these 4:
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks for splitting it out,
Conor.

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