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Message-Id: <169566184800.219467.13981427295646817430.b4-ty@arm.com>
Date: Mon, 25 Sep 2023 18:10:51 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] arm64/fp: Remove vector length pseudo registers
On Wed, 13 Sep 2023 15:48:11 +0100, Mark Brown wrote:
> Since the pseudo registers used by the cpufeature code for the maximum
> SVE and SME vector length appear to be unneeded other than as a double
> check of the full vector length enumeration. As discussed when fixing
> warnings from the pseudo register code let's simplify things by just
> removing those registers and relying entirely on the full enumeration.
>
>
> [...]
Applied to arm64 (for-next/sve-remove-pseudo-regs), thanks!
[1/2] arm64/sve: Remove ZCR pseudo register from cpufeature code
https://git.kernel.org/arm64/c/abef0695f966
[2/2] arm64/sve: Remove SMCR pseudo register from cpufeature code
https://git.kernel.org/arm64/c/391208485c3a
--
Catalin
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