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Message-Id: <20230925133859.1735879-2-apatel@ventanamicro.com>
Date: Mon, 25 Sep 2023 19:08:51 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Paolo Bonzini <pbonzini@...hat.com>,
Atish Patra <atishp@...shpatra.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Shuah Khan <shuah@...nel.org>
Cc: Andrew Jones <ajones@...tanamicro.com>,
Mayuresh Chitale <mchitale@...tanamicro.com>,
devicetree@...r.kernel.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org,
Anup Patel <apatel@...tanamicro.com>
Subject: [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry
Add an entry for the XVentanaCondOps extension to the
riscv,isa-extensions property.
Signed-off-by: Anup Patel <apatel@...tanamicro.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 36ff6749fbba..cad8ef68eca7 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,13 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: xventanacondops
+ description: |
+ The Ventana specific XVentanaCondOps extension for conditional
+ arithmetic and conditional-select/move operations defined by the
+ Ventana custom extensions specification v1.0.1 (or higher) at
+ https://github.com/ventanamicro/ventana-custom-extensions/releases.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
--
2.34.1
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