Message-ID: <20230925154929.2b6a9cab@bootlin.com>
Date:   Mon, 25 Sep 2023 15:50:49 +0200
From:   Herve Codina <herve.codina@...tlin.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
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        Paolo Abeni <pabeni@...hat.com>, Andrew Lunn <andrew@...n.ch>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
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        Mark Brown <broonie@...nel.org>,
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        Randy Dunlap <rdunlap@...radead.org>, netdev@...r.kernel.org,
        linuxppc-dev@...ts.ozlabs.org, devicetree@...r.kernel.org,
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        linux-arm-kernel@...ts.infradead.org, alsa-devel@...a-project.org,
        Simon Horman <horms@...nel.org>,
        Christophe JAILLET <christophe.jaillet@...adoo.fr>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v6 08/30] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc:
 Add support for QMC HDLC

On Mon, 25 Sep 2023 12:44:35 +0200
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> wrote:

> On 25/09/2023 12:27, Herve Codina wrote:
> > On Mon, 25 Sep 2023 10:21:15 +0200
> > Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> wrote:
> >   
> >> On 25/09/2023 10:17, Herve Codina wrote:  
> >>> Hi Krzysztof,
> >>>
> >>> On Sat, 23 Sep 2023 19:39:49 +0200
> >>> Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> wrote:
> >>>     
> >>>> On 22/09/2023 09:58, Herve Codina wrote:    
> >>>>> The QMC (QUICC mutichannel controller) is a controller present in some
> >>>>> PowerQUICC SoC such as MPC885.
> >>>>> The QMC HDLC uses the QMC controller to transfer HDLC data.
> >>>>>
> >>>>> Additionally, a framer can be connected to the QMC HDLC.
> >>>>> If present, this framer is the interface between the TDM bus used by the
> >>>>> QMC HDLC and the E1/T1 line.
> >>>>> The QMC HDLC can use this framer to get information about the E1/T1 line
> >>>>> and configure the E1/T1 line.
> >>>>>
> >>>>> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> >>>>> ---
> >>>>>  .../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml      | 24 +++++++++++++++++++
> >>>>>  1 file changed, 24 insertions(+)
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> >>>>> index 82d9beb48e00..61dfd5ef7407 100644
> >>>>> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> >>>>> @@ -101,6 +101,27 @@ patternProperties:
> >>>>>            Channel assigned Rx time-slots within the Rx time-slots routed by the
> >>>>>            TSA to this cell.
> >>>>>  
> >>>>> +      compatible:
> >>>>> +        const: fsl,qmc-hdlc      
> >>>>
> >>>> Why this is not a device/SoC specific compatible?    
> >>>
> >>> This compatible is present in a QMC channel.
> >>> The parent node (the QMC itself) contains a compatible with device/SoC:
> >>> --- 8< ---
> >>>   compatible:
> >>>     items:
> >>>       - enum:
> >>>           - fsl,mpc885-scc-qmc
> >>>           - fsl,mpc866-scc-qmc
> >>>       - const: fsl,cpm1-scc-qmc
> >>> --- 8< ---
> >>>
> >>> At the child level (ie QMC channel), I am not sure that adding device/SoC
> >>> makes sense. This compatible indicates that the QMC channel is handled by
> >>> the QMC HDLC driver.
> >>> At this level, whatever the device/SoC, we have to be QMC compliant.
> >>>
> >>> With these details, do you still think I need to change the child (channel)
> >>> compatible ?    
> >>
> >> From OS point of view, you have a driver binding to this child-level
> >> compatible. How do you enforce Linux driver binding based on parent
> >> compatible? I looked at your next patch and I did not see it.  
> > 
> > We do not need to have the child driver binding based on parent.  
> 
> Exactly, that's what I said.
> 
> > We have to ensure that the child handles a QMC channel and the parent provides
> > a QMC channel.
> > 
> > A QMC controller (parent) has to implement the QMC API (include/soc/fsl/qe/qmc.h)
> > and a QMC channel driver (child) has to use the QMC API.  
> 
> How does this solve my concerns? Sorry, I do not understand. Your driver
> is a platform driver and binds to the generic compatible. How do you
> solve regular compatibility issues (need for quirks) if parent
> compatible is not used?
> 
> How does being QMC compliant affects driver binding and
> compatibility/quirks?
> 
> We are back to my original question and I don't think you answered to
> any of the concerns.

Well, to be sure that I understand correctly, do you mean that I should
provide a compatible for the child (HDLC) with something like this:
--- 8< ---
  compatible:
    items:
      - enum:
          - fsl,mpc885-qmc-hdlc
          - fsl,mpc866-qmc-hdlc
      - const: fsl,cpm1-qmc-hdlc
      - const: fsl,qmc-hdlc
--- 8< ---

If so, I didn't do that because a QMC channel consumer (driver matching
fsl,qmc-hdlc) doesn't contains any SoC specific part.
It uses the channel as a communication channel to send/receive HDLC frames
to/from this communication channel.
All the specific SoC part is handled by the QMC controller (parent) itself and
not by any consumer (child).

Best regards,
Hervé

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