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Message-ID: <20230925-4a65c32623adcdf50c496005@orel>
Date: Mon, 25 Sep 2023 16:12:10 +0200
From: Andrew Jones <ajones@...tanamicro.com>
To: Anup Patel <apatel@...tanamicro.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>,
Atish Patra <atishp@...shpatra.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Shuah Khan <shuah@...nel.org>,
Mayuresh Chitale <mchitale@...tanamicro.com>,
devicetree@...r.kernel.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry
On Mon, Sep 25, 2023 at 07:08:53PM +0530, Anup Patel wrote:
> Add an entry for the Zicond extension to the riscv,isa-extensions property.
>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cad8ef68eca7..3f0b47686080 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -225,6 +225,12 @@ properties:
> ratified in the 20191213 version of the unprivileged ISA
> specification.
>
> + - const: zicond
> + description:
> + The standard Zicond extension for conditional arithmetic and
> + conditional-select/move operations as ratified in commit 95cf1f9
> + ("Add changes requested by Ved during signoff") of riscv-zicond.
> +
> - const: zicsr
> description: |
> The standard Zicsr extension for control and status register
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
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