| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAHAQgRC2xeqUu4mDZRJd3brcPNT4KovX65rNE7YXm+ku0+eERg@mail.gmail.com>
Date: Thu, 28 Sep 2023 07:39:45 +0800
From: Chen Wang <unicornxw@...il.com>
To: Conor Dooley <conor@...nel.org>
Cc: aou@...s.berkeley.edu, chao.wei@...hgo.com,
devicetree@...r.kernel.org, guoren@...nel.org, jszhang@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, palmer@...belt.com,
paul.walmsley@...ive.com, robh+dt@...nel.org,
xiaoguang.xing@...hgo.com, apatel@...tanamicro.com
Subject: Re: [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
Conor Dooley <conor@...nel.org> 于2023年9月28日周四 00:09写道：
>
> Hey,
>
> On Wed, Sep 27, 2023 at 04:54:38PM +0800, Chen Wang wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Now only support basic uart drivers to boot up into a basic console.
> >
> > Thanks,
> > Chen
> >
> > ---
> >
> > Changes in v3:
> > The patch series is based on v6.6-rc1. You can simply review or test
> > the patches at the link [5].
> > - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
> > - updated maintainers info. for sophgo devicetree
> > - remove the quirk changes for uart
> > - updated dts, such as:
> > - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
> > - update l2 cache node's name
> > - remove memory and pmu nodes
> > - fixed other issues as per input from reviewers.
>
> v3 looks better indeed. I had some comments on the bindings and dt
> patches, but none were particularly major.
>
> Thanks,
> Conor.
>
Thanks, Conor, I will continue imrpoving according to your commnents.
> >
> > Changes in v2:
> > The patch series is based on v6.6-rc1. You can simply review or test
> > the patches at the link [4].
> > - Improve format for comment of commitments as per input from last review.
> > - Improve format of DTS as per input from last review.
> > - Remove numa related stuff from DTS. This part is just for optimization, may
> > add it later if really needed.
> >
> > Changes in v1:
> > The patch series is based on v6.6-rc1. Due to it is not sent in thread,
> > I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
> > quick reference. You can simply review or test the patches at the link [3].
> >
> > [1]: https://milkv.io/pioneer
> > [2]: https://en.sophgo.com/product/introduce/sg2042.html
> > [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> > [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> > [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> > [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> > [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> > [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> > [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> > [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> > [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> > [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> > [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> > [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> > [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> > [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> > [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> > [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> >
> > ---
> >
> > Chen Wang (9):
> > riscv: Add SOPHGO SOC family Kconfig support
> > dt-bindings: vendor-prefixes: add milkv/sophgo
> > dt-bindings: riscv: add sophgo sg2042 bindings
> > dt-bindings: riscv: Add T-HEAD C920 compatibles
> > dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
> > MAINTAINERS: add two files to sophgo devicetrees entry
> > riscv: dts: add initial Sophgo SG2042 SoC device tree
> > riscv: dts: sophgo: add Milk-V Pioneer board device tree
> > riscv: defconfig: enable SOPHGO SoC
> >
> > Inochi Amaoto (2):
> > dt-bindings: timer: Add Sophgo sg2042 CLINT timer
> > dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
> >
> > .../sifive,plic-1.0.0.yaml | 1 +
> > .../sophgo,sg2042-clint-mswi.yaml | 42 +
> > .../devicetree/bindings/riscv/cpus.yaml | 1 +
> > .../devicetree/bindings/riscv/sophgo.yaml | 28 +
> > .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +
> > .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> > MAINTAINERS | 9 +
> > arch/riscv/Kconfig.socs | 5 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/sophgo/Makefile | 3 +
> > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++
> > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
> > arch/riscv/configs/defconfig | 1 +
> > 14 files changed, 2361 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> > create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> > create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> >
> >
> > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> > --
> > 2.25.1
> >
Powered by blists - more mailing lists