linux-kernel - [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

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Message-Id: <f7e71c60389973eea49e9e97ca50fc8c9c34e637.1695804418.git.unicornxw@gmail.com>
Date:   Wed, 27 Sep 2023 17:01:01 +0800
From:   Chen Wang <unicornxw@...il.com>
To:     aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
        devicetree@...r.kernel.org, guoren@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, robh+dt@...nel.org,
        xiaoguang.xing@...hgo.com, apatel@...tanamicro.com
Cc:     Chen Wang <unicornxw@...il.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Chen Wang <wangchen20@...as.ac.cn>
Subject: [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.

Acked-by: Chao Wei <chao.wei@...hgo.com>
Reviewed-by: Guo Ren <guoren@...nel.org>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Chen Wang <wangchen20@...as.ac.cn>
Signed-off-by: Chen Wang <unicornxw@...il.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:
-- 
2.25.1