linux-kernel - [PATCH] clocksource/drivers/riscv: Increase the clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 28 Sep 2023 11:45:20 +0100
From:   Prabhakar <prabhakar.csengg@...il.com>
To:     Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>
Cc:     Samuel Holland <samuel@...lland.org>,
        Anup Patel <anup@...infault.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Biju Das <biju.das.jz@...renesas.com>,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-renesas-soc@...r.kernel.org,
        Prabhakar <prabhakar.csengg@...il.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH] clocksource/drivers/riscv: Increase the clock_event rating

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Renesas RZ/Five SoC has OSTM blocks which can be used for clock_event and
clocksource [0]. The clock_event rating for the OSTM is set 300 but
whereas the rating for riscv-timer clock_event is set to 100 due to which
the kernel is choosing OSTM for clock_event.

As riscv-timer is much more efficient than MMIO clock_event, increase the
rating to 400 so that the kernel prefers riscv-timer over the MMIO based
clock_event.

[0] drivers/clocksource/renesas-ostm.c

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
Note, Ive set the rating similar to RISC-V clocksource, on ARM architecture
the rating for clk_event is set to 450.
---
 drivers/clocksource/timer-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index da3071b387eb..e4fc5da119a2 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -54,7 +54,7 @@ static unsigned int riscv_clock_event_irq;
 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
 	.name			= "riscv_timer_clockevent",
 	.features		= CLOCK_EVT_FEAT_ONESHOT,
-	.rating			= 100,
+	.rating			= 400,
 	.set_next_event		= riscv_clock_next_event,
 };
 
-- 
2.34.1