linux-kernel - Re: [PATCH V6] PCI: qcom: Fix broken pcie enumeration for 2_3

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Date:   Fri, 29 Sep 2023 15:48:12 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Sricharan Ramabadhran <quic_srichara@...cinc.com>
Cc:     agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
        robh@...nel.org, mani@...nel.org, lpieralisi@...nel.org,
        bhelgaas@...gle.com, kw@...ux.com, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        gregkh@...uxfoundation.org, dmitry.baryshkov@...aro.org,
        stable@...r.kernel.org, robimarko@...il.com
Subject: Re: [PATCH V6] PCI: qcom: Fix broken pcie enumeration for 2_3_3
 configs ops

On Tue, Sep 19, 2023 at 03:59:48PM +0530, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for qcom_pcie_post_init_2_3_3.
> PCIe slave address space size register offset is 0x358, but was wrongly
> changed to 0x16c as a part of commit 39171b33f652 ("PCI: qcom: Remove
> PCIE20_ prefix from register definitions"). Fixing it, by using the right
> macro and remove the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
> 
> Without this access to the registers of slave addr space like iATU etc
> are broken leading to PCIe enumeration failure on IPQ8074.
> 
> Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
> Cc: <Stable@...r.kernel.org>
> Reviewed-by: Manivannan Sadhasivam <mani@...nel.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> Tested-by: Robert Marko <robimarko@...il.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>

Applied to for-linus for v6.6, thanks!

> ---
>  [V6] Fixed subject and commit text as per Bjorn Helgaas
> 
>  drivers/pci/controller/dwc/pcie-qcom.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index e2f29404c84e..64420ecc24d1 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -43,7 +43,6 @@
>  #define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> @@ -797,8 +796,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
>  	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>  	u32 val;
>  
> -	writel(SLV_ADDR_SPACE_SZ,
> -		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
> +	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
>  
>  	val = readl(pcie->parf + PARF_PHY_CTRL);
>  	val &= ~PHY_TEST_PWR_DOWN;
> -- 
> 2.34.1
>