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Message-ID: <202309300620.S7uwOfcg-lkp@intel.com>
Date: Sat, 30 Sep 2023 07:13:06 +0800
From: kernel test robot <lkp@...el.com>
To: Michael Kelley <mikelley@...rosoft.com>, kys@...rosoft.com,
haiyangz@...rosoft.com, wei.liu@...nel.org, decui@...rosoft.com,
tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, hpa@...or.com, luto@...nel.org,
peterz@...radead.org, thomas.lendacky@....com,
sathyanarayanan.kuppuswamy@...ux.intel.com,
kirill.shutemov@...ux.intel.com, seanjc@...gle.com,
rick.p.edgecombe@...el.com, linux-kernel@...r.kernel.org,
linux-hyperv@...r.kernel.org, x86@...nel.org
Cc: oe-kbuild-all@...ts.linux.dev, mikelley@...rosoft.com
Subject: Re: [PATCH 3/5] x86/mm: Mark CoCo VM pages not present while
changing encrypted state
Hi Michael,
kernel test robot noticed the following build errors:
[auto build test ERROR on tip/master]
[also build test ERROR on tip/auto-latest linus/master v6.6-rc3 next-20230929]
[cannot apply to tip/x86/mm tip/x86/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Michael-Kelley/x86-coco-Use-slow_virt_to_phys-in-page-transition-hypervisor-callbacks/20230930-041800
base: tip/master
patch link: https://lore.kernel.org/r/1696011549-28036-4-git-send-email-mikelley%40microsoft.com
patch subject: [PATCH 3/5] x86/mm: Mark CoCo VM pages not present while changing encrypted state
config: i386-tinyconfig (https://download.01.org/0day-ci/archive/20230930/202309300620.S7uwOfcg-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230930/202309300620.S7uwOfcg-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309300620.S7uwOfcg-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/x86/mm/pat/set_memory.c: In function '__set_memory_enc_pgtable':
>> arch/x86/mm/pat/set_memory.c:2200:16: error: implicit declaration of function 'set_memory_p'; did you mean 'set_memory_np'? [-Werror=implicit-function-declaration]
2200 | return set_memory_p(&addr, numpages);
| ^~~~~~~~~~~~
| set_memory_np
cc1: some warnings being treated as errors
vim +2200 arch/x86/mm/pat/set_memory.c
2132
2133 /*
2134 * __set_memory_enc_pgtable() is used for the hypervisors that get
2135 * informed about "encryption" status via page tables.
2136 */
2137 static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
2138 {
2139 pgprot_t empty = __pgprot(0);
2140 struct cpa_data cpa;
2141 int ret;
2142
2143 /* Should not be working on unaligned addresses */
2144 if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr))
2145 addr &= PAGE_MASK;
2146
2147 memset(&cpa, 0, sizeof(cpa));
2148 cpa.vaddr = &addr;
2149 cpa.numpages = numpages;
2150
2151 /*
2152 * The caller must ensure that the memory being transitioned between
2153 * encrypted and decrypted is not being accessed. But if
2154 * load_unaligned_zeropad() touches the "next" page, it may generate a
2155 * read access the caller has no control over. To ensure such accesses
2156 * cause a normal page fault for the load_unaligned_zeropad() handler,
2157 * mark the pages not present until the transition is complete. We
2158 * don't want a #VE or #VC fault due to a mismatch in the memory
2159 * encryption status, since paravisor configurations can't cleanly do
2160 * the load_unaligned_zeropad() handling in the paravisor.
2161 *
2162 * There's no requirement to do so, but for efficiency we can clear
2163 * _PAGE_PRESENT and set/clr encryption attr as a single operation.
2164 */
2165 cpa.mask_set = enc ? pgprot_encrypted(empty) : pgprot_decrypted(empty);
2166 cpa.mask_clr = enc ? pgprot_decrypted(__pgprot(_PAGE_PRESENT)) :
2167 pgprot_encrypted(__pgprot(_PAGE_PRESENT));
2168 cpa.pgd = init_mm.pgd;
2169
2170 /* Must avoid aliasing mappings in the highmem code */
2171 kmap_flush_unused();
2172 vm_unmap_aliases();
2173
2174 /* Flush the caches as needed before changing the encryption attr. */
2175 if (x86_platform.guest.enc_cache_flush_required())
2176 cpa_flush(&cpa, 1);
2177
2178 ret = __change_page_attr_set_clr(&cpa, 1);
2179 if (ret)
2180 return ret;
2181
2182 /*
2183 * After clearing _PAGE_PRESENT and changing the encryption attribute,
2184 * we need to flush TLBs to ensure no further accesses to the memory can
2185 * be made with the old encryption attribute (but no need to flush caches
2186 * again). We could just use cpa_flush_all(), but in case TLB flushing
2187 * gets optimized in the cpa_flush() path use the same logic as above.
2188 */
2189 cpa_flush(&cpa, 0);
2190
2191 /* Notify hypervisor that we have successfully set/clr encryption attr. */
2192 if (!x86_platform.guest.enc_status_change_finish(addr, numpages, enc))
2193 return -EIO;
2194
2195 /*
2196 * Now that the hypervisor is sync'ed with the page table changes
2197 * made here, add back _PAGE_PRESENT. set_memory_p() does not flush
2198 * the TLB.
2199 */
> 2200 return set_memory_p(&addr, numpages);
2201 }
2202
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