linux-kernel - [PATCH 3/8] arm64: dts: qcom: ipq5332: Add USB Super-Speed PHY node

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Message-ID: <20230929084209.3033093-4-quic_ipkumar@quicinc.com>
Date:   Fri, 29 Sep 2023 14:12:04 +0530
From:   Praveenkumar I <quic_ipkumar@...cinc.com>
To:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <gregkh@...uxfoundation.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <p.zabel@...gutronix.de>,
        <geert+renesas@...der.be>, <arnd@...db.de>,
        <neil.armstrong@...aro.org>, <nfraprado@...labora.com>,
        <u-kumar1@...com>, <peng.fan@....com>, <quic_wcheng@...cinc.com>,
        <quic_varada@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-usb@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     <quic_kathirav@...cinc.com>, <quic_nsekar@...cinc.com>,
        <quic_srichara@...cinc.com>
Subject: [PATCH 3/8] arm64: dts: qcom: ipq5332: Add USB Super-Speed PHY node

Add USB Super-Speed UNIPHY node and populate the phandle on
gcc node for the parent clock map.

Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index d3fef2f80a81..b08ffd8c094e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -158,6 +158,29 @@ usbphy0: phy@...00 {
 			status = "disabled";
 		};
 
+		usbphy1: phy@...000 {
+			compatible = "qcom,ipq5332-usb-uniphy";
+			reg = <0x4b0000 0x800>;
+
+			clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB0_PIPE_CLK>;
+			clock-names = "ahb",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets =  <&gcc GCC_USB0_PHY_BCR>;
+
+			#clock-cells = <0>;
+			clock-output-names = "usb0_pipe_clk_src";
+
+			qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		qfprom: efuse@...00 {
 			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
 			reg = <0x000a4000 0x721>;
@@ -200,7 +223,7 @@ gcc: clock-controller@...0000 {
 				 <&sleep_clk>,
 				 <0>,
 				 <0>,
-				 <0>;
+				 <&usbphy1>;
 		};
 
 		tcsr_mutex: hwlock@...5000 {
-- 
2.34.1