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Message-ID: <20231002-askew-stoppable-9f83d23a2e93@spud>
Date: Mon, 2 Oct 2023 13:19:51 +0100
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Anup Patel <anup@...infault.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
Inochi Amaoto <inochiama@...look.com>, chao.wei@...hgo.com,
xiaoguang.xing@...hgo.com
Subject: Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device
tree
On Sat, Sep 30, 2023 at 08:39:36PM +0800, Jisheng Zhang wrote:
> + plic: interrupt-controller@...00000 {
> + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
This fails dtbs_check, the compatible you added to the binding is
cv1800-plic.
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
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