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Message-ID: <ZRvCoc8miXAjSenM@gmail.com>
Date:   Tue, 3 Oct 2023 09:28:33 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Nathan Chancellor <nathan@...nel.org>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        linux-kernel@...r.kernel.org, x86@...nel.org, acdunlap@...gle.com,
        ashok.raj@...el.com, bp@...en8.de, david@...hat.com,
        dionnaglaze@...gle.com, hpa@...or.com, jacobhxu@...gle.com,
        jgross@...e.com, jroedel@...e.de, khalid.elmously@...onical.com,
        kim.phillips@....com, kirill.shutemov@...ux.intel.com,
        llvm@...ts.linux.dev, luto@...nel.org, mingo@...hat.com,
        nikunj@....com, peterz@...radead.org, pgonda@...gle.com,
        rientjes@...gle.com, rppt@...nel.org, seanjc@...gle.com,
        tglx@...utronix.de, thomas.lendacky@....com
Subject: Re: [PATCH] x86/boot: Move x86_cache_alignment initialization to
 correct spot


* Nathan Chancellor <nathan@...nel.org> wrote:

> On Mon, Oct 02, 2023 at 03:00:45PM -0700, Dave Hansen wrote:
> > c->x86_cache_alignment is initialized from c->x86_clflush_size.
> > However, commit fbf6449f84bf moved c->x86_clflush_size initialization
> > to later in boot without moving the c->x86_cache_alignment assignment.
> > 
> > This presumably left c->x86_cache_alignment set to zero for longer
> > than it should be.
> > 
> > The result was an oops on 32-bit kernels while accessing a pointer
> > at 0x20.  The 0x20 came from accessing a structure member at offset
> > 0x10 (buffer->cpumask) from a ZERO_SIZE_PTR=0x10.  kmalloc() can
> > evidently return ZERO_SIZE_PTR when it's given 0 as its alignment
> > requirement.
> > 
> > Move the c->x86_cache_alignment initialization to be after
> > c->x86_clflush_size has an actual value.
> > 
> > Fixes: fbf6449f84bf ("x86/sev-es: Set x86_virt_bits to the correct value straight away, instead of a two-phase approach")
> > Cc: Adam Dunlap <acdunlap@...gle.com>
> > Cc: Ingo Molnar <mingo@...nel.org>
> > Cc: Jacob Xu <jacobhxu@...gle.com>
> > Link: https://lore.kernel.org/all/20231002200426.GA4127272@dev-arch.thelio-3990X/
> 
> Tested-by: Nathan Chancellor <nathan@...nel.org>
> 
> Thanks for the quick fix!

Thanks for the quick testing - I've applied this fix on top
of fbf6449f84bf in tip:x86/mm.

Dave, I've added your SOB - let me know if that's not OK:

  Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>

Thanks,

	Ingo

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