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Message-ID: <CAEPPPKtf6mo7YrUYdT57TiTjWO=NJ61aMDR0W-D2z95EJxQppQ@mail.gmail.com>
Date: Tue, 3 Oct 2023 17:22:36 +0800
From: Sophon Wu <wuxilin123@...il.com>
To: neil.armstrong@...aro.org
Cc: Andy Gross <agross@...nel.org>, andersson@...nel.org,
devicetree@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, mturquette@...libre.com,
Rob Herring <robh+dt@...nel.org>, sboyd@...nel.org
Subject: Re: [PATCH v3 3/3] clk: qcom: add SM8550 DISPCC driver
<neil.armstrong@...aro.org> 于2023年10月3日周二 15:16写道:
>
> Hi,
>
> On 03/10/2023 04:17, Sophon Wu wrote:
> > On 09/01/2023 16:47, Neil Armstrong wrote:
> >
> >> Add support for the display clock controller found in SM8550
> >> based devices.
> >
> >> This clock controller feeds the Multimedia Display SubSystem (MDSS).
> >> This driver is based on the SM8450 support.
> >
> >> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> >> ---
> >
> > Hi Neil,
> >
> > I'm trying to enable display on SM8550 but having trouble with clocks. Do you
> > have any idea on this maybe? Full dmesg here: https://bpa.st/7E6Q
>
> You may need to remove the cont-splash memory zone and the simple-framebuffer,
> if you leave the cont-splash the bootloader will leave the MDSS on and Linux
> will fail to take over and initialize the clocks.
>
> This is known issue, and for now we re-initialize everything from Linux after
> ABL disables the display subsystem entirely.
>
> Neil
It works! Thanks a lot for the tip.
Regards,
Xilin
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