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Message-ID: <20231003120846.28626-2-quic_nsekar@quicinc.com>
Date: Tue, 3 Oct 2023 17:38:41 +0530
From: Nitheesh Sekar <quic_nsekar@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <lpieralisi@...nel.org>,
<kw@...ux.com>, <robh@...nel.org>, <bhelgaas@...gle.com>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<vkoul@...nel.org>, <kishon@...nel.org>, <mani@...nel.org>,
<p.zabel@...gutronix.de>, <quic_nsekar@...cinc.com>,
<quic_srichara@...cinc.com>, <quic_varada@...cinc.com>,
<quic_ipkumar@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>
Subject: [PATCH 1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018.
Signed-off-by: Nitheesh Sekar <quic_nsekar@...cinc.com>
---
.../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
new file mode 100644
index 000000000000..6b2574f9532e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,uniphy-pcie-28lp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY driver
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@...cinc.com>
+ - Sricharan Ramabadhran <quic_srichara@...cinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5018-uniphy-pcie-gen2x1
+ - qcom,ipq5018-uniphy-pcie-gen2x2
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pipe_clk
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy
+ - const: phy_phy
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - resets
+ - reset-names
+ - clocks
+ - clock-names
+ - "#phy-cells"
+ - "#clock-cells"
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+ phy@...00 {
+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x2";
+ reg = <0x86000 0x800>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie0_pipe_clk";
+ assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ assigned-clock-rates = <125000000>;
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy", "phy_phy";
+ };
--
2.17.1
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