linux-kernel - Re: [PATCH v4 6/6] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 3 Oct 2023 18:25:22 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc:     vireshk@...nel.org, nm@...com, sboyd@...nel.org,
        myungjoo.ham@...sung.com, kyungmin.park@...sung.com,
        cw00.choi@...sung.com, andersson@...nel.org,
        konrad.dybcio@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        jejb@...ux.ibm.com, martin.petersen@...cle.com,
        alim.akhtar@...sung.com, avri.altman@....com, bvanassche@....org,
        linux-scsi@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        quic_asutoshd@...cinc.com, quic_cang@...cinc.com,
        quic_nitirawa@...cinc.com, quic_narepall@...cinc.com,
        quic_bhaskarv@...cinc.com, quic_richardp@...cinc.com,
        quic_nguyenb@...cinc.com, quic_ziqichen@...cinc.com,
        bmasney@...hat.com, krzysztof.kozlowski@...aro.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 6/6] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC

On Tue, 3 Oct 2023 at 14:16, Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org> wrote:
>
> UFS host controller, when scaling gears, should choose appropriate
> performance state of RPMh power domain controller along with clock
> frequency. So let's add the OPP table support to specify both clock
> frequency and RPMh performance states replacing the old "freq-table-hz"
> property.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++++++++++++++++++++-------
>  1 file changed, 30 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index a4e58ad731c3..33abd84aae53 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2198,21 +2198,42 @@ ufs_mem_hc: ufshc@...4000 {
>                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> -                       freq-table-hz =
> -                               <37500000 300000000>,
> -                               <0 0>,
> -                               <0 0>,
> -                               <37500000 300000000>,
> -                               <0 0>,
> -                               <0 0>,
> -                               <0 0>,
> -                               <0 0>;
> +
> +                       operating-points-v2 = <&ufs_opp_table>;
>
>                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
>                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
>                         interconnect-names = "ufs-ddr", "cpu-ufs";
>
>                         status = "disabled";
> +
> +                       ufs_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-37500000 {
> +                                       opp-hz = /bits/ 64 <37500000>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <37500000>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>;

I must say I still consider this to be uglier than hard coding clock
names in the driver.

> +                                       required-opps = <&rpmhpd_opp_low_svs>;
> +                               };
> +
> +                               opp-300000000 {
> +                                       opp-hz = /bits/ 64 <300000000>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <300000000>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>,
> +                                                /bits/ 64 <0>;
> +                                       required-opps = <&rpmhpd_opp_nom>;
> +                               };
> +                       };
>                 };
>
>                 ufs_mem_phy: phy@...7000 {
> --
> 2.25.1
>


-- 
With best wishes
Dmitry