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Message-ID: <CAMuHMdWLoPUZw-HBsk3bELmfyTC-wF9q3CN-ouexR-Nvfqjkzw@mail.gmail.com>
Date:   Wed, 4 Oct 2023 10:45:09 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Claudiu <claudiu.beznea@...on.dev>
Cc:     mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        linus.walleij@...aro.org, gregkh@...uxfoundation.org,
        jirislaby@...nel.org, magnus.damm@...il.com,
        catalin.marinas@....com, will@...nel.org,
        quic_bjorande@...cinc.com, konrad.dybcio@...aro.org, arnd@...db.de,
        neil.armstrong@...aro.org, prabhakar.mahadev-lad.rj@...renesas.com,
        biju.das.jz@...renesas.com, linux-renesas-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 07/28] clk: renesas: rzg2l: add support for RZ/G3S PLL

On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Add support for reading the frequency of PLL1/4/6 available on RZ/G3S.
> The computation formula for PLL frequency is as follows:
> Fout = (nir + nfr / 4096) * Fin / (mr * pr)
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>
> Changes in v2:
> - added GENMASK() defines for DIV_P, DIV_M, DIV_NI, DIV_NF
> - used mul_u64_u32_shr() as suggested by Geert on v1
> - s/CLK_TYPE_G3S_SAM_PLL/CLK_TYPE_G3S_PLL/g

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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