Message-ID: <20231004151405.521596-1-cleger@rivosinc.com>
Date:   Wed,  4 Oct 2023 17:13:57 +0200
From:   Clément Léger <cleger@...osinc.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>
Cc:     Clément Léger <cleger@...osinc.com>,
        Atish Patra <atishp@...osinc.com>,
        Andrew Jones <ajones@...tanamicro.com>,
        Evan Green <evan@...osinc.com>,
        Björn Topel <bjorn@...osinc.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Ron Minnich <rminnich@...il.com>,
        Daniel Maslowski <cyrevolt@...glemail.com>,
        Conor Dooley <conor@...nel.org>
Subject: [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode

Since commit 61cadb9 ("Provide new description of misaligned load/store
behavior compatible with privileged architecture.") in the RISC-V ISA
manual, it is stated that misaligned load/store might not be supported.
However, the RISC-V kernel uABI describes that misaligned accesses are
supported. In order to support that, this series adds support for S-mode
handling of misaligned accesses as well support for prctl(PR_UNALIGN).

Handling misaligned access in kernel allows for a finer grain control
of the misaligned accesses behavior, and thanks to the prctl() call,
can allow disabling misaligned access emulation to generate SIGBUS. User
space can then optimize its software by removing such access based on
SIGBUS generation.

This series is useful when using a SBI implementation that does not
handle misaligned traps as well as detecting misaligned accesses
generated by userspace application using the prctrl(PR_SET_UNALIGN)
feature.

This series can be tested using the spike simulator[1] and a modified
openSBI version[2] which allows to always delegate misaligned load/store to
S-mode. A test[3] that exercise various instructions/registers can be
executed to verify the unaligned access support.

[1] https://github.com/riscv-software-src/riscv-isa-sim
[2] https://github.com/rivosinc/opensbi/tree/dev/cleger/no_misaligned
[3] https://github.com/clementleger/unaligned_test

Changes in V2:
 - Fix wrong fpu assembly function name (detected with llvm build)
 - Changes the detection mechanism using direct detection in trap handler
   (CONFIG_M_MODE does not support extable and re-adding extable just
    for some boot time detection is a bit overkill)
 - Fix commit order (used a variable introduce in a later commit)
 - Add a CONFIG_RISCV_MISALIGNED option to completely disable misaligned
   handling in kernel and reduce text size
 - Use for_each_present_cpu() instead of for_each_possible_cpu() in init
 - Ensure that if unaligned_ctl was set, fail to online cpu if it does
   not emulate misaligned accesses.

Clément Léger (8):
  riscv: remove unused functions in traps_misaligned.c
  riscv: add support for misaligned trap handling in S-mode
  riscv: report perf event for misaligned fault
  riscv: add floating point insn support to misaligned access emulation
  riscv: add support for sysctl unaligned_enabled control
  riscv: annotate check_unaligned_access_boot_cpu() with __init
  riscv: report misaligned accesses emulation to hwprobe
  riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN

 arch/riscv/Kconfig                    |   9 +
 arch/riscv/include/asm/cpufeature.h   |  18 ++
 arch/riscv/include/asm/entry-common.h |  14 +
 arch/riscv/include/asm/processor.h    |   9 +
 arch/riscv/kernel/Makefile            |   2 +-
 arch/riscv/kernel/cpufeature.c        |   6 +-
 arch/riscv/kernel/fpu.S               | 121 +++++++++
 arch/riscv/kernel/process.c           |  18 ++
 arch/riscv/kernel/smpboot.c           |   2 +-
 arch/riscv/kernel/traps.c             |   9 -
 arch/riscv/kernel/traps_misaligned.c  | 375 ++++++++++++++++++++++----
 11 files changed, 524 insertions(+), 59 deletions(-)

-- 
2.42.0

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