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Message-ID: <46de1eb3-c237-2433-0ca7-ebeff47abc1a@arm.com>
Date: Thu, 5 Oct 2023 17:39:00 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: James Clark <james.clark@....com>, coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.linux.dev,
broonie@...nel.org, maz@...nel.org
Cc: Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>,
Zenghui Yu <yuzenghui@...wei.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Mike Leach <mike.leach@...aro.org>,
Leo Yan <leo.yan@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Anshuman Khandual <anshuman.khandual@....com>,
Rob Herring <robh@...nel.org>,
Jintack Lim <jintack.lim@...aro.org>,
Akihiko Odaki <akihiko.odaki@...nix.com>,
Fuad Tabba <tabba@...gle.com>, Joey Gouly <joey.gouly@....com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/6] arm64/sysreg: Move TRFCR definitions to sysreg
On 05/10/2023 13:57, James Clark wrote:
> Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX.
> This also mirrors the previous definition so no code change is required.
>
> Also add TRFCR_EL12 which will start to be used in a later commit.
>
> Reviewed-by: Mark Brown <broonie@...nel.org>
> Signed-off-by: James Clark <james.clark@....com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>
> ---
> arch/arm64/include/asm/sysreg.h | 12 ----------
> arch/arm64/tools/sysreg | 41 +++++++++++++++++++++++++++++++++
> 2 files changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 38296579a4fd..068dd6abe273 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -278,8 +278,6 @@
> #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>
> -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
> -
> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>
> #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
> @@ -496,7 +494,6 @@
> #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
> #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
>
> -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
> #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
> #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
> @@ -904,15 +901,6 @@
> /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
> #define SYS_MPIDR_SAFE_VAL (BIT(31))
>
> -#define TRFCR_ELx_TS_SHIFT 5
> -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
> -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
> -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
> -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
> -#define TRFCR_EL2_CX BIT(3)
> -#define TRFCR_ELx_ExTRE BIT(1)
> -#define TRFCR_ELx_E0TRE BIT(0)
> -
> /* GIC Hypervisor interface registers */
> /* ICH_MISR_EL2 bit definitions */
> #define ICH_MISR_EOI (1 << 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 2517ef7c21cf..2104152db18e 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2624,3 +2624,44 @@ Field 5 F
> Field 4 P
> Field 3:0 Align
> EndSysreg
> +
> +SysregFields TRFCR_EL2
> +Res0 63:7
> +UnsignedEnum 6:5 TS
> + 0b0000 USE_TRFCR_EL1_TS
> + 0b0001 VIRTUAL
> + 0b0010 GUEST_PHYSICAL
> + 0b0011 PHYSICAL
> +EndEnum
> +Res0 4
> +Field 3 CX
> +Res0 2
> +Field 1 E2TRE
> +Field 0 E0HTRE
> +EndSysregFields
> +
> +# TRFCR_EL1 doesn't have the CX bit so redefine it without CX instead of
> +# using a shared definition between TRFCR_EL2 and TRFCR_EL1
> +SysregFields TRFCR_ELx
> +Res0 63:7
> +UnsignedEnum 6:5 TS
> + 0b0001 VIRTUAL
> + 0b0010 GUEST_PHYSICAL
> + 0b0011 PHYSICAL
> +EndEnum
> +Res0 4:2
> +Field 1 ExTRE
> +Field 0 E0TRE
> +EndSysregFields
> +
> +Sysreg TRFCR_EL1 3 0 1 2 1
> +Fields TRFCR_ELx
> +EndSysreg
> +
> +Sysreg TRFCR_EL2 3 4 1 2 1
> +Fields TRFCR_EL2
> +EndSysreg
> +
> +Sysreg TRFCR_EL12 3 5 1 2 1
> +Fields TRFCR_ELx
> +EndSysreg
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