linux-kernel - [PATCH v3 0/5] irqchip/gic-v3: Enable non-coherent GIC designs probing

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Message-Id: <20231006125929.48591-1-lpieralisi@kernel.org>
Date:   Fri,  6 Oct 2023 14:59:24 +0200
From:   Lorenzo Pieralisi <lpieralisi@...nel.org>
To:     linux-kernel@...r.kernel.org
Cc:     Lorenzo Pieralisi <lpieralisi@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-acpi@...r.kernel.org, Mark Rutland <mark.rutland@....com>,
        Robin Murphy <robin.murphy@....com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Fang Xiang <fangxiang3@...omi.com>,
        Marc Zyngier <maz@...nel.org>
Subject: [PATCH v3 0/5] irqchip/gic-v3: Enable non-coherent GIC designs probing

This series is v3 of previous series:

v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kernel.org
v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org

v2 -> v3:
	- Added ACPICA temporary changes and ACPI changes to implement
	  ECR https://bugzilla.tianocore.org/show_bug.cgi?id=4557
	- ACPI changes are for testing purposes - subject to ECR code
	  first approval

v1 -> v2:
	- Updated DT bindings as per feedback
	- Updated patch[2] to use GIC quirks infrastructure

Original cover letter
---
The GICv3 architecture specifications provide a means for the
system programmer to set the shareability and cacheability
attributes the GIC components (redistributors and ITSes) use
to drive memory transactions.

Albeit the architecture give control over shareability/cacheability
memory transactions attributes (and barriers), it is allowed to
connect the GIC interconnect ports to non-coherent memory ports
on the interconnect, basically tying off shareability/cacheability
"wires" and de-facto making the redistributors and ITSes non-coherent
memory observers.

This series aims at starting a discussion over a possible solution
to this problem, by adding to the GIC device tree bindings the
standard dma-noncoherent property. The GIC driver uses the property
to force the redistributors and ITSes shareability attributes to
non-shareable, which consequently forces the driver to use CMOs
on GIC memory tables.

On ARM DT DMA is default non-coherent, so the GIC driver can't rely
on the generic DT dma-coherent/non-coherent property management layer
(of_dma_is_coherent()) which would default all GIC designs in the field
as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling.

When a consistent approach is agreed upon for DT an equivalent binding will
be put forward for ACPI based systems.

Lorenzo Pieralisi (4):
  dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent
    property
  irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing
  ACPICA: Add new MADT GICC/GICR/ITS flags handling [code first]
  irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing

Marc Zyngier (1):
  irqchip/gic-v3-its: Split allocation from initialisation of its_node

 .../interrupt-controller/arm,gic-v3.yaml      |  12 ++
 drivers/acpi/processor_core.c                 |  21 +++
 drivers/irqchip/irq-gic-common.h              |  12 ++
 drivers/irqchip/irq-gic-v3-its.c              | 174 +++++++++++-------
 drivers/irqchip/irq-gic-v3.c                  |  22 +++
 include/acpi/actbl2.h                         |  11 +-
 include/linux/acpi.h                          |   3 +
 7 files changed, 189 insertions(+), 66 deletions(-)

-- 
2.34.1