linux-kernel - Re: [PATCH v2] mtd: micron-st: enable lock/unlock for mt25qu512a

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f0a7acb3-00b5-433d-af5c-724a509fb816@linaro.org>
Date:   Fri, 6 Oct 2023 14:33:11 +0100
From:   Tudor Ambarus <tudor.ambarus@...aro.org>
To:     SHUKLA Mamta Ramendra <mamta.shukla@...ca-geosystems.com>,
        "pratyush@...nel.org" <pratyush@...nel.org>,
        "michael@...le.cc" <michael@...le.cc>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        "richard@....at" <richard@....at>,
        "vigneshr@...com" <vigneshr@...com>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Cc:     GEO-CHHER-bsp-development 
        <bsp-development.geo@...ca-geosystems.com>
Subject: Re: [PATCH v2] mtd: micron-st: enable lock/unlock for mt25qu512a


Hi,

Thanks for the debugging info.

On 10/6/23 11:30, SHUKLA Mamta Ramendra wrote:

cut

> --------------------------------------------------------
> 
> IMO, HAS_16BIT_SR flag is causing lock/unlock failure,
> since BP bits are calculated wrong then.
> 
> I tested also for a case where I don't parse SFDP and
> reverted the condition in  micron_st_nor_default_init()
> for 16BIT Status Register Flag. And lock/unlock fails with
> same log as Non-working case.
> 
> And this mt25qu512 has 8-BIT SR as typical micron-st flash.
> 

Indeed, the problem is that HAS_16BIT_SR gets set when it shouldn't have
to. This means that the BFPT table of the flash is wrong and we should
fix the parsed settings via a post_bfpt hook.

Does the following fix your problem?

diff --git a/drivers/mtd/spi-nor/micron-st.c
b/drivers/mtd/spi-nor/micron-st.c
index 4afcfc57c896..733bbddc6829 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -180,6 +180,17 @@ static const struct flash_info micron_nor_parts[] = {
        },
 };

+static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
+                               const struct sfdp_parameter_header
*bfpt_header,
+                               const struct sfdp_bfpt *bfpt)
+{
+       nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+}
+
+static struct spi_nor_fixups mt25qu512a_fixups = {
+       .post_bfpt = mt25qu512a_post_bfpt_fixup,
+}
+
 static const struct flash_info st_nor_parts[] = {
        {
                .name = "m25p05-nonjedec",
@@ -405,10 +416,10 @@ static const struct flash_info st_nor_parts[] = {
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
                .name = "mt25qu512a",
-               .size = SZ_64M,
-               .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ,
-               .fixup_flags = SPI_NOR_4B_OPCODES,
+               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_4BIT_BP |
+                        SPI_NOR_BP3_SR_BIT6,
                .mfr_flags = USE_FSR,
+               .fixups = &mt25qu512a_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x20),
                .name = "n25q512a",


If yes, please add some prints in sfdp.c to determine where it's set,
either in BFPT_DWORD15_QER_SR2_BIT1 or BFPT_DWORD15_QER_SR2_BIT1_NO_RD

Is the datasheet for this flash public? Would you send me a link to it
please?

Cheers,
ta