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Message-Id: <0783d4e9c9fcea8a84a8a7245f87168d4b698149.1696663037.git.unicorn_wang@outlook.com>
Date: Sat, 7 Oct 2023 15:55:27 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
devicetree@...r.kernel.org, guoren@...nel.org, jszhang@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, palmer@...belt.com,
paul.walmsley@...ive.com, robh+dt@...nel.org,
xiaoguang.xing@...hgo.com, apatel@...tanamicro.com
Cc: Chen Wang <unicorn_wang@...look.com>,
Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v5 04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles
From: Chen Wang <unicorn_wang@...look.com>
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.
Acked-by: Chao Wei <chao.wei@...hgo.com>
Reviewed-by: Guo Ren <guoren@...nel.org>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
+ - thead,c920
- const: riscv
- items:
- enum:
--
2.25.1
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