linux-kernel - [irqchip: irq/irqchip-fixes] irqchip/riscv-intc: Mark all INTC nodes as initialized

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Sat, 07 Oct 2023 12:00:44 -0000
From:   "irqchip-bot for Anup Patel" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Dmitry Dunaev <dunaev@...on.ru>,
        Anup Patel <apatel@...tanamicro.com>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-fixes] irqchip/riscv-intc: Mark all INTC nodes
 as initialized

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     e13cd66bd821be417c498a34928652db4ac6b436
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/e13cd66bd821be417c498a34928652db4ac6b436
Author:        Anup Patel <apatel@...tanamicro.com>
AuthorDate:    Tue, 03 Oct 2023 10:13:51 +05:30
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Sat, 07 Oct 2023 12:47:12 +01:00

irqchip/riscv-intc: Mark all INTC nodes as initialized

The RISC-V INTC local interrupts are per-HART (or per-CPU) so we
create INTC IRQ domain only for the INTC node belonging to the boot
HART. This means only the boot HART INTC node will be marked as
initialized and other INTC nodes won't be marked which results
downstream interrupt controllers (such as PLIC, IMSIC and APLIC
direct-mode) not being probed due to missing device suppliers.

To address this issue, we mark all INTC node for which we don't
create IRQ domain as initialized.

Reported-by: Dmitry Dunaev <dunaev@...on.ru>
Signed-off-by: Anup Patel <apatel@...tanamicro.com>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20230926102801.1591126-1-dunaev@tecon.ru
Link: https://lore.kernel.org/r/20231003044403.1974628-4-apatel@ventanamicro.com
---
 drivers/irqchip/irq-riscv-intc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 4adeee1..e8d01b1 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node,
 	 * for each INTC DT node. We only need to do INTC initialization
 	 * for the INTC DT node belonging to boot CPU (or boot HART).
 	 */
-	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
+	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) {
+		/*
+		 * The INTC nodes of each CPU are suppliers for downstream
+		 * interrupt controllers (such as PLIC, IMSIC and APLIC
+		 * direct-mode) so we should mark an INTC node as initialized
+		 * if we are not creating IRQ domain for it.
+		 */
+		fwnode_dev_initialized(of_fwnode_handle(node), true);
 		return 0;
+	}
 
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }