linux-kernel - Re: linux-next: Tree for Oct 6 (riscv: andes)

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Message-ID: <ff4bbd33-e494-4db2-93e2-59d1a866d7cf@infradead.org>
Date:   Sat, 7 Oct 2023 09:06:33 -0700
From:   Randy Dunlap <rdunlap@...radead.org>
To:     Conor Dooley <conor@...nel.org>
Cc:     Stephen Rothwell <sfr@...b.auug.org.au>,
        Linux Next Mailing List <linux-next@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>
Subject: Re: linux-next: Tree for Oct 6 (riscv: andes)

Hi Conor,

On 10/7/23 03:56, Conor Dooley wrote:
> On Fri, Oct 06, 2023 at 05:28:27PM -0700, Randy Dunlap wrote:
>>
>>
>> On 10/5/23 21:38, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Changes since 20231005:
>>>
>>
>> on riscv 64bit:
>>
>> WARNING: unmet direct dependencies detected for ERRATA_ANDES
>>   Depends on [n]: RISCV_ALTERNATIVE [=n] && RISCV_SBI [=y]
>>   Selected by [y]:
>>   - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_SBI [=y]
>>
>> ../arch/riscv/errata/andes/errata.c:59:54: warning: 'struct alt_entry' declared inside parameter list will not be visible outside of this definition or declaration
>>    59 | void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>>       |                                                      ^~~~~~~~~
>>
>>
>> Full randconfig file is attached.
> 
> Riiight. XIP_KERNEL is enabled, which means no alternatives are
> permitted, but that R9A config option selects the Andes errata, which in
> turn depends on alternatives.
> 
> I suppose we could do something like (untested):
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> index 7b74de732718..6fe85255e2ce 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -343,7 +343,7 @@ config ARCH_R9A07G043
>         select ARCH_RZG2L
>         select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
>         select DMA_GLOBAL_POOL
> -       select ERRATA_ANDES if RISCV_SBI
> +       select ERRATA_ANDES if (RISCV_SBI & RISCV_ALTERNATIVE)

s/&/&&/ and then this works. Thanks.

Acked-by: Randy Dunlap <rdunlap@...radead.org>
Tested-by: Randy Dunlap <rdunlap@...radead.org>

>         select ERRATA_ANDES_CMO if ERRATA_ANDES
>         help
>           This enables support for the Renesas RZ/Five SoC.

-- 
~Randy