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Message-ID: <b8dca5f4-533d-4a9c-a177-fbdf3ad7848a@amd.com>
Date:   Mon, 9 Oct 2023 09:56:41 -0500
From:   Terry Bowman <Terry.Bowman@....com>
To:     Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Robert Richter <rrichter@....com>
Cc:     Alison Schofield <alison.schofield@...el.com>,
        Vishal Verma <vishal.l.verma@...el.com>,
        Ira Weiny <ira.weiny@...el.com>,
        Ben Widawsky <bwidawsk@...nel.org>,
        Dan Williams <dan.j.williams@...el.com>,
        Davidlohr Bueso <dave@...olabs.net>,
        Dave Jiang <dave.jiang@...el.com>, linux-cxl@...r.kernel.org,
        linux-kernel@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for
 logging protocol errors



On 10/2/23 09:56, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:33 +0200
> Robert Richter <rrichter@....com> wrote:
> 
>> From: Terry Bowman <terry.bowman@....com>
>>
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need to
>> be virtually memory mapped before enabling interrupts. Create the
>> initializer function devm_cxl_setup_parent_dport() for this when the
>> endpoint is connected with the dport. The initialization sets up the
>> RCH RAS and AER mappings.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
>> the RCH downstream port's AER and RAS registers.
>>
>> Co-developed-by: Robert Richter <rrichter@....com>
>> Signed-off-by: Terry Bowman <terry.bowman@....com>
> As before. Co-dev just before SoB. 
> 
> https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L521
> This example looks like what you have here.
> 
>> Signed-off-by: Robert Richter <rrichter@....com>
> Otherwise, LGTM
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

Yes, we will fix.

Regards,
Terry

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