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Message-ID: <20231011111438.909552-4-cleger@rivosinc.com>
Date: Wed, 11 Oct 2023 13:14:28 +0200
From: Clément Léger <cleger@...osinc.com>
To: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Cc: Clément Léger <cleger@...osinc.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Albert Ou <aou@...s.berkeley.edu>,
Jonathan Corbet <corbet@....net>,
Andrew Jones <ajones@...tanamicro.com>,
Evan Green <evan@...osinc.com>, Conor Dooley <conor@...nel.org>
Subject: [PATCH v1 03/13] riscv: hwprobe: export Zv* ISA extensions
Export Zv* ISA extensions that were added in "RISC-V Cryptography
Extensions Volume II" specification[1] through hwprobe. This adds
support for the following instructions:
- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.
[1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Signed-off-by: Clément Léger <cleger@...osinc.com>
---
Documentation/riscv/hwprobe.rst | 48 +++++++++++++++++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 16 +++++++++
arch/riscv/kernel/sys_riscv.c | 19 +++++++++++
3 files changed, 83 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index a52996b22f75..edfed33669ea 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -77,6 +77,54 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
in version 1.0 of the Bit-Manipulation ISA extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKN`: The Zvkn extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNC`: The Zvknc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNG`: The Zvkng extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKS`: The Zvks extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSC`: The Zvksc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSG`: The Zvksg extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 006bfb48343d..d868eb431cd6 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -29,6 +29,22 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 6)
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 7)
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 8)
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 9)
+#define RISCV_HWPROBE_EXT_ZVKN (1 << 10)
+#define RISCV_HWPROBE_EXT_ZVKNC (1 << 11)
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 12)
+#define RISCV_HWPROBE_EXT_ZVKNG (1 << 13)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 14)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 15)
+#define RISCV_HWPROBE_EXT_ZVKS (1 << 16)
+#define RISCV_HWPROBE_EXT_ZVKSC (1 << 17)
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 18)
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 19)
+#define RISCV_HWPROBE_EXT_ZVKSG (1 << 20)
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 21)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5ce593ce07a4..4f5e51c192d5 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -156,6 +156,25 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZBA);
CHECK_ISA_EXT(ZBB);
CHECK_ISA_EXT(ZBS);
+
+ if (has_vector()) {
+ CHECK_ISA_EXT(ZVBB);
+ CHECK_ISA_EXT(ZVBC);
+ CHECK_ISA_EXT(ZVKB);
+ CHECK_ISA_EXT(ZVKG);
+ CHECK_ISA_EXT(ZVKN);
+ CHECK_ISA_EXT(ZVKNC);
+ CHECK_ISA_EXT(ZVKNED);
+ CHECK_ISA_EXT(ZVKNG);
+ CHECK_ISA_EXT(ZVKNHA);
+ CHECK_ISA_EXT(ZVKNHB);
+ CHECK_ISA_EXT(ZVKS);
+ CHECK_ISA_EXT(ZVKSC);
+ CHECK_ISA_EXT(ZVKSED);
+ CHECK_ISA_EXT(ZVKSH);
+ CHECK_ISA_EXT(ZVKSG);
+ CHECK_ISA_EXT(ZVKT);
+ }
#undef CHECK_ISA_EXT
}
--
2.42.0
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