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Message-ID: <9a831a6e-ab5e-4911-8011-f6eb82dd3d6a@linaro.org>
Date: Thu, 12 Oct 2023 21:46:26 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jacky Huang <ychuang570808@...il.com>, linus.walleij@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, p.zabel@...gutronix.de, j.neuschaefer@....net
Cc: linux-arm-kernel@...ts.infradead.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
schung@...oton.com, Jacky Huang <ychuang3@...oton.com>
Subject: Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1
On 11/10/2023 11:05, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@...oton.com>
>
> Add 'pinctrl' node and 'gpioa' ~ 'gpion' nodes to the dtsi of ma35d1
> SoC and describe default pin configurations.
>
> Enable all UART nodes presented on som and iot boards, and add pinctrl
> function settings to these nodes.
>
> Signed-off-by: Jacky Huang <ychuang3@...oton.com>
> ---
> .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 83 ++++++++-
> .../boot/dts/nuvoton/ma35d1-som-256m.dts | 86 ++++++++-
> arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 175 +++++++++++++++++-
> 3 files changed, 335 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> index b89e2be6abae..ff0d2bf8f5bf 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> @@ -14,6 +14,10 @@ / {
>
> aliases {
> serial0 = &uart0;
> + serial10 = &uart10;
> + serial12 = &uart12;
> + serial13 = &uart13;
> + serial14 = &uart14;
> };
>
> chosen {
> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
> };
> };
>
> -&uart0 {
> - status = "okay";
> -};
> -
> &clk {
> assigned-clocks = <&clk CAPLL>,
> <&clk DDRPLL>,
> @@ -54,3 +54,78 @@ &clk {
> "integer",
> "integer";
> };
> +
> +&pinctrl {
> + uart0 {
> + pinctrl_uart0: uart0grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
> + <MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
> + };
> + };
> +
> + uart10 {
> + pinctrl_uart10: uart10grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPH_L 16 2 &pcfg_default>,
> + <MA35_SYS_REG_GPH_L 20 2 &pcfg_default>,
> + <MA35_SYS_REG_GPH_L 24 2 &pcfg_default>,
> + <MA35_SYS_REG_GPH_L 28 2 &pcfg_default>;
> + };
> + };
> +
> + uart12 {
> + pinctrl_uart12: uart12grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPC_H 20 2 &pcfg_default>,
> + <MA35_SYS_REG_GPC_H 24 2 &pcfg_default>,
> + <MA35_SYS_REG_GPC_H 28 2 &pcfg_default>;
> + };
> + };
> +
> + uart13 {
> + pinctrl_uart13: uart13grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPH_H 16 3 &pcfg_default>,
> + <MA35_SYS_REG_GPH_H 20 3 &pcfg_default>;
> + };
> + };
> +
> + uart14 {
> + pinctrl_uart14: uart14grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
> + <MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart0>;
> + status = "okay";
> +};
> +
> +&uart10 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart10>;
> + status = "okay";
> +};
> +
> +&uart12 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart12>;
> + status = "okay";
> +};
> +
> +&uart13 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart13>;
> + status = "okay";
> +};
> +
> +&uart14 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart14>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> index a1ebddecb7f8..c8c26f37116b 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> @@ -14,6 +14,10 @@ / {
>
> aliases {
> serial0 = &uart0;
> + serial11 = &uart11;
> + serial12 = &uart12;
> + serial14 = &uart14;
> + serial16 = &uart16;
> };
>
> chosen {
> @@ -33,10 +37,6 @@ clk_hxt: clock-hxt {
> };
> };
>
> -&uart0 {
> - status = "okay";
> -};
> -
> &clk {
> assigned-clocks = <&clk CAPLL>,
> <&clk DDRPLL>,
> @@ -54,3 +54,81 @@ &clk {
> "integer",
> "integer";
> };
> +
> +&pinctrl {
> + uart0 {
> + pinctrl_uart0: uart0grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
> + <MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
This does not look like generic pinctrl bindings. Looks
over-complicated. From where did you get it? Which recent bindings and
drivers where used as an example? Register addresses should be in the
driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
this is not really suitable for DTS.
> + };
> + };
> +
> + uart11 {
> + pinctrl_uart11: uart11grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPL_L 0 2 &pcfg_default>,
> + <MA35_SYS_REG_GPL_L 4 2 &pcfg_default>,
> + <MA35_SYS_REG_GPL_L 8 2 &pcfg_default>,
> + <MA35_SYS_REG_GPL_L 12 2 &pcfg_default>;
> + };
> + };
> +
> + uart12 {
> + pinctrl_uart12: uart12grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPI_L 4 2 &pcfg_default>,
> + <MA35_SYS_REG_GPI_L 8 2 &pcfg_default>,
> + <MA35_SYS_REG_GPI_L 12 2 &pcfg_default>;
> + };
> + };
> +
> + uart14 {
> + pinctrl_uart14: uart14grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPI_L 20 2 &pcfg_default>,
> + <MA35_SYS_REG_GPI_L 24 2 &pcfg_default>,
> + <MA35_SYS_REG_GPI_L 28 2 &pcfg_default>;
> + };
> + };
> +
> + uart16 {
> + pinctrl_uart16: uart16grp {
> + nuvoton,pins =
> + <MA35_SYS_REG_GPK_L 0 2 &pcfg_default>,
> + <MA35_SYS_REG_GPK_L 4 2 &pcfg_default>,
> + <MA35_SYS_REG_GPK_L 8 2 &pcfg_default>,
> + <MA35_SYS_REG_GPK_L 12 2 &pcfg_default>;
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart0>;
> + status = "okay";
> +};
> +
> +&uart11 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart11>;
> + status = "okay";
> +};
> +
> +&uart12 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart12>;
> + status = "okay";
> +};
> +
> +&uart14 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart14>;
> + status = "okay";
> +};
> +
> +&uart16 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart16>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> index 781cdae566a0..85431a074ab2 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
> +#include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
>
> / {
> compatible = "nuvoton,ma35d1";
> @@ -83,7 +84,7 @@ soc {
> ranges;
>
> sys: system-management@...60000 {
> - compatible = "nuvoton,ma35d1-reset";
> + compatible = "nuvoton,ma35d1-reset", "syscon";
> reg = <0x0 0x40460000 0x0 0x200>;
> #reset-cells = <1>;
> };
> @@ -95,6 +96,178 @@ clk: clock-controller@...60200 {
> clocks = <&clk_hxt>;
> };
>
> + pinctrl: pinctrl@...40000 {
> + compatible = "nuvoton,ma35d1-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nuvoton,sys = <&sys>;
> + ranges = <0x0 0x0 0x40040000 0xc00>;
> +
> + gpioa: gpioa@...40000 {
> + reg = <0x0 0x40>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPA_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiob: gpiob@...40040 {
> + reg = <0x40 0x40>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPB_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpioc: gpioc@...40080 {
> + reg = <0x80 0x40>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPC_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiod: gpiod@...400c0 {
> + reg = <0xc0 0x40>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPD_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpioe: gpioe@...40100 {
> + reg = <0x100 0x40>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPE_GATE>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiof: gpiof@...40140 {
> + reg = <0x140 0x40>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPF_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiog: gpiog@...40180 {
> + reg = <0x180 0x40>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPG_GATE>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpioh: gpioh@...401c0 {
> + reg = <0x1c0 0x40>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPH_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpioi: gpioi@...40200 {
> + reg = <0x200 0x40>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPI_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpioj: gpioj@...40240 {
> + reg = <0x240 0x40>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPJ_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiok: gpiok@...40280 {
> + reg = <0x280 0x40>;
> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPK_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiol: gpiol@...402c0 {
> + reg = <0x2c0 0x40>;
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPL_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpiom: gpiom@...40300 {
> + reg = <0x300 0x40>;
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPM_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpion: gpion@...40340 {
> + reg = <0x340 0x40>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPN_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pcfg_default: pcfg-default {
> + slew-rate = <0>;
> + input-schmitt-disable;
> + bias-disable;
> + power-source = <3300>;
> + drive-strength = <0>;
> + };
> +
> + pcfg_emac_3_3v: pcfg-emac-3.3v {
Drop, unused.
> + slew-rate = <0>;
> + input-schmitt-enable;
> + bias-disable;
> + power-source = <3300>;
> + drive-strength = <1>;
> + };
> +
> + pcfg_emac_1_8v: pcfg-emac-1.8v {
Drop, unused.
> + slew-rate = <0>;
> + input-schmitt-enable;
> + bias-disable;
> + power-source = <1800>;
> + drive-strength = <1>;
> + };
> + };
> +
> uart0: serial@...00000 {
> compatible = "nuvoton,ma35d1-uart";
> reg = <0x0 0x40700000 0x0 0x100>;
Best regards,
Krzysztof
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