linux-kernel - Re: [PATCH v2 2/4] mtd: rawnand: NAND controller write protect

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Message-ID: <20231012090805.7af1e8e0@xps-13>
Date:   Thu, 12 Oct 2023 09:08:05 +0200
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     dregan@...l.com
Cc:     bcm-kernel-feedback-list@...adcom.com,
        linux-mtd@...ts.infradead.org, f.fainelli@...il.com,
        rafal@...ecki.pl, joel.peshkin@...adcom.com,
        computersforpeace@...il.com, dan.beygelman@...adcom.com,
        william.zhang@...adcom.com, frieder.schrempf@...tron.de,
        linux-kernel@...r.kernel.org, vigneshr@...com, richard@....at,
        bbrezillon@...nel.org, kdasu.kdev@...il.com,
        JaimeLiao <jaimeliao.tw@...il.com>,
        Arseniy Krasnov <AVKrasnov@...rdevices.ru>,
        Adam Borowski <kilobyte@...band.pl>
Subject: Re: [PATCH v2 2/4] mtd: rawnand: NAND controller write protect

Hi dregan@...l.com,

dregan@...l.com wrote on Thu, 12 Oct 2023 02:41:10 +0200:

> Allow NAND controller to be responsible for write protect pin
> handling during fast path and exec_op destructive operation
> when controller_wp flag is set.
> 
> Signed-off-by: David Regan <dregan@...l.com>
> 
> ---
> 
> Changes in v2: none
> ---
>  drivers/mtd/nand/raw/nand_base.c | 4 ++++
>  include/linux/mtd/rawnand.h      | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index 47cc2c35153b..38ed0ced5b8e 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -367,6 +367,10 @@ static int nand_check_wp(struct nand_chip *chip)
>  	if (chip->options & NAND_BROKEN_XD)
>  		return 0;
> 
> +	/* controller responsible for NAND write protect */
> +	if (chip->controller->controller_wp)
> +		return 0;
> +
>  	/* Check the WP bit */
>  	ret = nand_status_op(chip, &status);
>  	if (ret)
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index 31aceda8616c..f03b9d7f48b8 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -1111,6 +1111,7 @@ struct nand_controller_ops {
>   *			the bus without restarting an entire read operation nor
>   *			changing the column.
>   * @supported_op.cont_read: The controller supports sequential cache reads.
> + * @controller_wp:	controller responsible for NAND write protect.

			The controller is in charge of handling the WP pin

>   */
>  struct nand_controller {
>  	struct mutex lock;
> @@ -1119,6 +1120,7 @@ struct nand_controller {
>  		unsigned int data_only_read: 1;
>  		unsigned int cont_read: 1;
>  	} supported_op;
> +	bool controller_wp;
>  };
> 
>  static inline void nand_controller_init(struct nand_controller *nfc)
> --
> 2.37.3
> 
> 


Thanks,
Miquèl