linux-kernel - Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

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Message-ID: <20231012-gratuity-siesta-b9e06b11be43@spud>
Date:   Thu, 12 Oct 2023 10:41:45 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Inochi Amaoto <inochiama@...look.com>
Cc:     Chen Wang <unicorn_wang@...look.com>,
        Chao Wei <chao.wei@...hgo.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Jisheng Zhang <jszhang@...nel.org>, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC
 device tree

On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
> >On 2023/10/9 19:26, Inochi Amaoto wrote:
> >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
> >> ---
> >>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
> >>   1 file changed, 36 insertions(+)
> >>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> new file mode 100644
> >> index 000000000000..3864d34b0100
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> @@ -0,0 +1,36 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/*
> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@...look.com>
> >> + */
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >This include is not required.
> 
> Thx.

I can drop this include on application. Is the rest of the series okay
with you Chen Wang?

Thanks,
Conor.

> 
> >> +#include "cv180x.dtsi"
> >> +
> >> +/ {
> >> +    compatible = "sophgo,cv1812h";
> >> +
> >> +    memory@...00000 {
> >> +        device_type = "memory";
> >> +        reg = <0x80000000 0x10000000>;
> >> +    };
> >What's this defined for , I see this is different against cv1800b.
> 
> CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
> size is different. I write this node here because the RAM is embedded
> and fixed size, and leave it in the board DT is unnecessary.
> 
> >> +
> >> +    soc {
> >> +        interrupt-parent = <&plic>;
> >> +
> >> +        plic: interrupt-controller@...00000 {
> >> +            compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> >> +            reg = <0x70000000 0x4000000>;
> >> +            interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> >> +            interrupt-controller;
> >> +            #address-cells = <0>;
> >> +            #interrupt-cells = <2>;
> >> +            riscv,ndev = <101>;
> >> +        };
> >> +
> >> +        clint: timer@...00000 {
> >> +            compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> >> +            reg = <0x74000000 0x10000>;
> >> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> >> +        };
> >> +    };
> >> +};
> >> --
> >> 2.42.0
> >>
> >

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