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Message-ID: <20231012095736.100784-14-angelogioacchino.delregno@collabora.com>
Date: Thu, 12 Oct 2023 11:57:33 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: chunkuang.hu@...nel.org
Cc: p.zabel@...gutronix.de, airlied@...il.com, daniel@...ll.ch,
matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com,
dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, wenst@...omium.org,
kernel@...labora.com, ehristev@...labora.com,
nfraprado@...labora.com,
"Jason-JH . Lin" <jason-jh.lin@...iatek.com>,
Alexandre Mergnat <amergnat@...libre.com>,
CK Hu <ck.hu@...iatek.com>
Subject: [PATCH v11 13/16] drm/mediatek: gamma: Program gamma LUT type for descending or rising
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Reviewed-by: Jason-JH.Lin <jason-jh.lin@...iatek.com>
Reviewed-by: Alexandre Mergnat <amergnat@...libre.com>
Reviewed-by: CK Hu <ck.hu@...iatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 6746033615db..0f116c0e51b5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -22,6 +22,7 @@
#define GAMMA_RELAY_MODE BIT(0)
#define GAMMA_LUT_EN BIT(1)
#define GAMMA_DITHERING BIT(2)
+#define GAMMA_LUT_TYPE BIT(2)
#define DISP_GAMMA_SIZE 0x0030
#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16)
#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0)
@@ -82,6 +83,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev)
return 0;
}
+static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size)
+{
+ u64 first, last;
+ int last_entry = lut_size - 1;
+
+ first = lut[0].red + lut[0].green + lut[0].blue;
+ last = lut[last_entry].red + lut[last_entry].green + lut[last_entry].blue;
+
+ return !!(first > last);
+}
+
/*
* SoCs supporting 12-bits LUTs are using a new register layout that does
* always support (by HW) both 12-bits and 10-bits LUT but, on those, we
@@ -173,6 +185,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
cfg_val = readl(gamma->regs + DISP_GAMMA_CFG);
+ if (!gamma->data->has_dither) {
+ /* Descending or Rising LUT */
+ if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1))
+ cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1);
+ else
+ cfg_val &= ~GAMMA_LUT_TYPE;
+ }
+
/* Enable the gamma table */
cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1);
--
2.42.0
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