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Message-ID: <9c2ec240-bca0-4f99-96db-a5156bbd82e5@loongson.cn>
Date:   Fri, 13 Oct 2023 19:12:09 +0800
From:   Sui Jingfeng <suijingfeng@...ngson.cn>
To:     Xi Ruoyao <xry111@...111.site>, WANG Xuerui <kernel@...0n.name>,
        Icenowy Zheng <uwu@...nowy.me>,
        Huacai Chen <chenhuacai@...nel.org>
Cc:     Andrew Morton <akpm@...ux-foundation.org>,
        Weihao Li <liweihao@...ngson.cn>,
        "Mike Rapoport (IBM)" <rppt@...nel.org>,
        Jun Yi <yijun@...ngson.cn>, Baoquan He <bhe@...hat.com>,
        "Matthew Wilcox (Oracle)" <willy@...radead.org>,
        David Hildenbrand <david@...hat.com>,
        Hongchen Zhang <zhanghongchen@...ngson.cn>,
        Binbin Zhou <zhoubinbin@...ngson.cn>,
        Zhen Lei <thunder.leizhen@...wei.com>,
        Tiezhu Yang <yangtiezhu@...ngson.cn>,
        Thomas Gleixner <tglx@...utronix.de>,
        Zhihong Dong <donmor3000@...mail.com>,
        loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] loongarch/mm: disable WUC for pgprot_writecombine as
 same as ioremap_wc

Hi,


On 2023/10/10 20:26, Xi Ruoyao wrote:
>> For DMA non-coherent buffers, we should try to implement arch-specific dma_map_ops,
>> invalidate the CPU cache and flush the CPU write buffer before the device do DMA. Instead
>> of pretend to be DMA coherent for all buffers, a kernel cmdline is not a system level
>> solution for all of GPU drivers and OS release.
> IIUC this is a hardware bug of 7A1000 and 7A2000, so the proper location
> of the workaround is in the bridge chip driver.  Or am I
> misunderstanding something?


The ls2k1000 and ls2k2000 SoC (which don't use with 7A1000 and 7A2000) are also suffer form this
problem. If this is a hardware bug of 7A1000 and 7A2000, why forbidden WC mapping of pages in
system RAM?

The problem of this patch and the <16c52e503043> commit is that it forbidden all WC mappings by
default. Even pages in system RAM.

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