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Message-ID: <0494c270-e3db-4621-88a6-313ccdb562ec@linaro.org>
Date: Fri, 13 Oct 2023 17:22:17 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Conor Dooley <conor@...nel.org>
Cc: Kris Chaplin <kris.chaplin@....com>, thomas.delev@....com,
michal.simek@....com, robh+dt@...nel.org, conor+dt@...nel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
git@....com
Subject: Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master
and MAINTAINERS entry
On 13/10/2023 17:07, Conor Dooley wrote:
>>> +maintainers:
>>> + - Kris Chaplin <kris.chaplin@....com>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: amd,axi-1wire-master
>>
>> That's a quite generic compatible. axi is ARM term, 1-wire is the name
>> of the bus and master is the role. Concatenating three common words does
>> not create unique device name. Compatibles are supposed to be specific
>> and this is really relaxed. Anything can be over AXI, everything in
>> 1wire is 1wire and every master device is a master.
>
> Given the vendor (and the title of the binding) this is almost certainly
> an FPGA IP core, so the generic name is understandable. Using the exact
> name of the IP in the AMD/Xilinx catalog probably is the best choice?
Other option is that it is a part of some Zynq SoC.
Best regards,
Krzysztof
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