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Message-ID: <20231016143805.GA1207929@bhelgaas>
Date: Mon, 16 Oct 2023 09:38:05 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Shuai Xue <xueshuai@...ux.alibaba.com>
Cc: chengyou@...ux.alibaba.com, kaishen@...ux.alibaba.com,
yangyicong@...wei.com, will@...nel.org,
Jonathan.Cameron@...wei.com, baolin.wang@...ux.alibaba.com,
robin.murphy@....com, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
rdunlap@...radead.org, mark.rutland@....com,
zhuo.song@...ux.alibaba.com, renyu.zj@...ux.alibaba.com
Subject: Re: [PATCH v7 3/4] drivers/perf: add DesignWare PCIe PMU driver
On Mon, Oct 16, 2023 at 11:00:13AM +0800, Shuai Xue wrote:
> On 2023/10/14 00:30, Bjorn Helgaas wrote:
> > On Fri, Oct 13, 2023 at 11:46:44AM +0800, Shuai Xue wrote:
> >> On 2023/10/13 00:25, Bjorn Helgaas wrote:
> >>> On Thu, Oct 12, 2023 at 11:28:55AM +0800, Shuai Xue wrote:
> >>>> This commit adds the PCIe Performance Monitoring Unit (PMU)
> >>>> driver support for T-Head Yitian SoC chip. Yitian is based on
> >>>> the Synopsys PCI Express Core controller IP which provides
> >>>> statistics feature. The PMU is not a PCIe Root Complex
> >>>> integrated End Point(RCiEP) device but only register counters
> >>>> provided by each PCIe Root Port.
> @@ -447,10 +447,10 @@ static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags)
> u32 ctrl;
>
> /* Only one counter and it is in use */
> - if (pcie_pmu->event)
> + if (pcie_pmu->event[type])
> return -ENOSPC;
>
> - pcie_pmu->event = event;
> + pcie_pmu->event[type] = event;
OK, makes good sense (probably update the comment also, e.g., "one
counter of each type").
> }
> > If so, I might word this as:
> >
> > Each Root Port contains one counter that can be used for either:
> >
> > - Time-Based Analysis (RX/TX data throughput and time spent in
> > each low-power LTSSM state) or
> >
> > - Event counting (error and non-error events for a specified lane)
> >
> > There is no interrupt for counter overflow.
>
> Based on above, I change the word to:
>
> To facilitate collection of statistics the controller provides the
> following two features for each Root Port:
>
> - one 64-bit counter for Time Based Analysis (RX/TX data throughput and
> time spent in each low-power LTSSM state) and
> - one 32-bit counter for Event counting (error and non-error events for
> a specified lane)
>
> Note: There is no interrupt for counter overflow.
Beautiful, that's very clear.
Bjorn
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