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Message-ID: <20231017131456.2053396-16-cleger@rivosinc.com>
Date: Tue, 17 Oct 2023 15:14:52 +0200
From: Clément Léger <cleger@...osinc.com>
To: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Cc: Clément Léger <cleger@...osinc.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Albert Ou <aou@...s.berkeley.edu>,
Jonathan Corbet <corbet@....net>,
Andrew Jones <ajones@...tanamicro.com>,
Evan Green <evan@...osinc.com>,
Conor Dooley <conor@...nel.org>,
Samuel Ortiz <sameo@...osinc.com>
Subject: [PATCH v2 15/19] riscv: hwprobe: export Zvfh[min] ISA extensions
Export Zvfh[min] ISA extension[1] through hwprobe.
Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Signed-off-by: Clément Léger <cleger@...osinc.com>
---
Documentation/riscv/hwprobe.rst | 8 ++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_riscv.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 9c909e0d5316..782ac26cb92a 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -146,6 +146,14 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
is supported as defined in the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index dc4eaa978ad1..79407010952a 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -52,6 +52,8 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZFH (1 << 26)
#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27)
#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28)
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 29)
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 84daaf6ed4a1..8d6edd721627 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -185,6 +185,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZVKSED);
CHECK_ISA_EXT(ZVKSH);
CHECK_ISA_EXT(ZVKT);
+ CHECK_ISA_EXT(ZVFH);
+ CHECK_ISA_EXT(ZVFHMIN);
}
if (has_fpu()) {
--
2.42.0
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