linux-kernel - Re: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <25ba377a-c590-1a1c-6be3-e268a6b300c9@arm.com>
Date:   Wed, 18 Oct 2023 10:42:01 -0500
From:   Jeremy Linton <jeremy.linton@....com>
To:     Marc Zyngier <maz@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, catalin.marinas@....com,
        will@...nel.org, mark.rutland@....com, anshuman.khandual@....com,
        krisman@...e.de, broonie@...nel.org, james.morse@....com,
        ionela.voinescu@....com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display
 enabled cores

On 10/18/23 07:43, Marc Zyngier wrote:
> On Tue, 17 Oct 2023 20:15:43 +0100,
> Jeremy Linton <jeremy.linton@....com> wrote:
>>
>> Hi,
>>
>> On 10/17/23 13:01, Marc Zyngier wrote:
>>> On Tue, 17 Oct 2023 06:23:22 +0100,
>>> Jeremy Linton <jeremy.linton@....com> wrote:
>>>>
>>>> Now that we have the ability to display the list of cores
>>>> with a feature when it is selectivly enabled, lets display the
>>>> cores enabled for 32-bit use at EL0.
>>>>
>>>> Signed-off-by: Jeremy Linton <jeremy.linton@....com>
>>>> ---
>>>>    arch/arm64/kernel/cpufeature.c | 15 +++++++++++++--
>>>>    1 file changed, 13 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>>>> index b7b67bac0e60..512cbe446b41 100644
>>>> --- a/arch/arm64/kernel/cpufeature.c
>>>> +++ b/arch/arm64/kernel/cpufeature.c
>>>> @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
>>>>    	if (!has_cpuid_feature(entry, scope))
>>>>    		return allow_mismatched_32bit_el0;
>>>>    -	if (scope == SCOPE_SYSTEM)
>>>> -		pr_info("detected: 32-bit EL0 Support\n");
>>>> +	if (scope == SCOPE_SYSTEM) {
>>>> +		struct arm64_cpu_capabilities *has_32bit;
>>>> +
>>>> +		has_32bit = (struct arm64_cpu_capabilities *)entry;
>>>> +
>>>> +		has_32bit->cpus = system_32bit_el0_cpumask();
>>>
>>> This seems rather dodgy. 'entry' comes from a static const array which
>>> will, in all likelihood be mapped R/O pretty soon after the initial
>>> CPU bringup. Try offlining/onlining a CPU and you should see a
>>> firework similar to what I have below (I hacked the CnP property, but
>>> that's no different from what you are doing):
>>
>> Yes, dodgy is a good word. The other choices, maintain a mask just for
>> the print or dump the static key and always use the cpu_32bit_el0_mask
>> or some combination, weren't much better in the "ick" category. If
>> anyone sees a better way I'm open to suggestion, although simply
>> dropping this last patch is fine too.
> 
> An obvious choice would be to replace the 'cpus' cpumask with a
> function that evaluates a cpumask stored separately.

Right, I was too busy trying to cleanup the 32-bit mask, that works too.