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Message-ID: <20231018055326.18256-5-jyanchou@realtek.com>
Date: Wed, 18 Oct 2023 13:53:24 +0800
From: Jyan Chou <jyanchou@...ltek.com>
To: <adrian.hunter@...el.com>, <ulf.hansson@...aro.org>,
<jh80.chung@...sung.com>
CC: <linux-mmc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<benchuanggli@...il.com>, <jyanchou@...ltek.com>
Subject: [PATCH V2][4/4] mmc: Add dt-bindings for realtek mmc driver
Document the device-tree bindings for Realtek SoCs mmc driver.
Signed-off-by: Jyan Chou <jyanchou@...ltek.com>
---
v0 -> v2:
- Add dt-binding.
---
---
.../bindings/mmc/realtek-dw-mshc.yaml | 119 ++++++++++++++++++
1 file changed, 119 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/realtek-dw-mshc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/realtek-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/realtek-dw-mshc.yaml
new file mode 100644
index 000000000000..f398a595c5c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/realtek-dw-mshc.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/realtek-dw-mshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek designware mobile storage host controller
+
+description:
+ Realtek uses the Synopsys designware mobile storage host controller
+ to interface a SoC with storage medium. This file documents the Realtek
+ specific extensions.
+
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+maintainers:
+ - Jyan Chou <jyanchou@...ltek.com>
+
+# Everything else is described in the common file
+properties:
+ compatible:
+ enum:
+ - realtek,rtd-dw-cqe-emmc
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+ description:
+ Handle to "biu" and "ciu" clocks for the bus interface unit clock and
+ the card interface unit clock.
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: biu
+ - const: ciu
+ - const: vp0
+ - const: vp1
+ description:
+ "vp0" and "vp1" are used to control the clock phases.
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: reset
+
+ speed-step:
+ maxItems: 1
+ description:
+ "speed-step" represents the bus speed mode of emmc. "3" means HS400,
+ "2" means HS200, "0" means HS.
+
+ pinctrl-names:
+ maxItems: 10
+ items:
+ - const: default
+ - const: sdr50
+ - const: ddr50
+ - const: hs200
+ - const: hs400
+ - const: tune0
+ - const: tune1
+ - const: tune2
+ - const: tune3
+ - const: tune4
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - pinctrl-names
+ - pinctrl
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ emmc: emmc@...00 {
+ compatible = "realtek,rtd-dw-cqe-emmc";
+ reg = <0x00012000 0x00600>,
+ <0x00012180 0x00060>;
+ reg-names = "emmc","cqhci";
+ interrupts = <0 42 4>;
+ clocks = <&cc RTD1319D_CRT_CLK_EN_EMMC>,
+ <&cc RTD1319D_CRT_CLK_EN_EMMC_IP>,
+ <&cc RTD1319D_CRT_PLL_EMMC_VP0>,
+ <&cc RTD1319D_CRT_PLL_EMMC_VP1>;
+ clock-names = "biu", "ciu", "vp0", "vp1";
+ clock-freq-min-max = <300000 400000000>;
+ clock-frequency = <400000>;
+ vmmc-supply = <®_vcc1v8>;
+ resets = <&cc RTD1319D_CRT_RSTN_EMMC>;
+ reset-names = "reset";
+ speed-step = <3>;
+ cqe = <1>;
+ pinctrl-names = "default", "sdr50", "ddr50", "hs200", "hs400", "tune0", "tune1", "tune2", "tune3", "tune4";
+ pinctrl-0 = <&emmc_pins_sdr50>;
+ pinctrl-1 = <&emmc_pins_sdr50>;
+ pinctrl-2 = <&emmc_pins_ddr50>;
+ pinctrl-3 = <&emmc_pins_hs200>;
+ pinctrl-4 = <&emmc_pins_hs400>;
+ pinctrl-5 = <&emmc_pins_tune0>;
+ pinctrl-6 = <&emmc_pins_tune1>;
+ pinctrl-7 = <&emmc_pins_tune2>;
+ pinctrl-8 = <&emmc_pins_tune3>;
+ pinctrl-9 = <&emmc_pins_tune4>;
+ };
--
2.42.0
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