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Message-ID: <20231019084452.11fd0645@xps-13>
Date: Thu, 19 Oct 2023 08:44:52 +0200
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Frank Li <Frank.Li@....com>
Cc: alexandre.belloni@...tlin.com, conor.culhane@...vaco.com,
imx@...ts.linux.dev, joe@...ches.com,
linux-i3c@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 Resent 6/6] i3c: master: svc: fix random hot join
failure since timeout error
Hi Frank,
Frank.Li@....com wrote on Wed, 18 Oct 2023 11:59:26 -0400:
> master side report:
> silvaco-i3c-master 44330000.i3c-master: Error condition: MSTATUS 0x020090c7, MERRWARN 0x00100000
>
> BIT 20: TIMEOUT error
> The module has stalled too long in a frame. This happens when:
> - The TX FIFO or RX FIFO is not handled and the bus is stuck in the
> middle of a message,
> - No STOP was issued and between messages,
> - IBI manual is used and no decision was made.
I am still not convinced this should be ignored in all cases.
Case 1 is a problem because the hardware failed somehow.
Case 2 is fine I guess.
Case 3 is not possible in Linux, this will not be supported.
> The maximum stall period is 10 KHz or 100 μs.
s/10 KHz//
>
> This is a just warning. System irq thread schedule latency is possible
> bigger than 100us. Just omit this waring.
This can be considered as being just a warning as the system IRQ
latency can easily be greater than 100us.
>
> Fixes: dd3c52846d59 ("i3c: master: svc: Add Silvaco I3C master driver")
> Cc: stable@...r.kernel.org
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
>
> Notes:
> Change from v1 to v2
> -none
>
> drivers/i3c/master/svc-i3c-master.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 1a57fdebaa26d..fedb31e0076c4 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -93,6 +93,7 @@
> #define SVC_I3C_MINTMASKED 0x098
> #define SVC_I3C_MERRWARN 0x09C
> #define SVC_I3C_MERRWARN_NACK BIT(2)
> +#define SVC_I3C_MERRWARN_TIMEOUT BIT(20)
> #define SVC_I3C_MDMACTRL 0x0A0
> #define SVC_I3C_MDATACTRL 0x0AC
> #define SVC_I3C_MDATACTRL_FLUSHTB BIT(0)
> @@ -226,6 +227,11 @@ static bool svc_i3c_master_error(struct svc_i3c_master *master)
> if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) {
> merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
> writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
> +
> + /* ignore timeout error */
> + if (merrwarn & SVC_I3C_MERRWARN_TIMEOUT)
> + return false;
> +
> dev_err(master->dev,
> "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
> mstatus, merrwarn);
Thanks,
Miquèl
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