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Message-ID: <001501da0282$a5b7a150$f126e3f0$@samsung.com>
Date: Thu, 19 Oct 2023 20:51:50 +0900
From: "Chanwoo Choi" <cw00.choi@...sung.com>
To: "'Sascha Hauer'" <s.hauer@...gutronix.de>,
<linux-rockchip@...ts.infradead.org>
Cc: <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
"'Heiko Stuebner'" <heiko@...ech.de>,
"'Chanwoo Choi'" <chanwoo@...nel.org>,
"'Kyungmin Park'" <kyungmin.park@...sung.com>,
"'MyungJoo Ham'" <myungjoo.ham@...sung.com>,
"'Will Deacon'" <will@...nel.org>,
"'Mark Rutland'" <mark.rutland@....com>, <kernel@...gutronix.de>,
"'Michael Riesch'" <michael.riesch@...fvision.net>,
"'Robin Murphy'" <robin.murphy@....com>,
"'Vincent Legoll'" <vincent.legoll@...il.com>,
"'Rob Herring'" <robh+dt@...nel.org>,
"'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@...aro.org>,
"'Conor Dooley'" <conor+dt@...nel.org>,
<devicetree@...r.kernel.org>,
"'Sebastian Reichel'" <sebastian.reichel@...labora.com>
Subject: RE: [PATCH v8 11/26] PM / devfreq: rockchip-dfi: Handle LPDDR2
correctly
> -----Original Message-----
> From: Sascha Hauer <s.hauer@...gutronix.de>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: linux-rockchip@...ts.infradead.org
> Cc: linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> linux-pm@...r.kernel.org; Heiko Stuebner <heiko@...ech.de>; Chanwoo Choi
> <chanwoo@...nel.org>; Kyungmin Park <kyungmin.park@...sung.com>; MyungJoo
> Ham <myungjoo.ham@...sung.com>; Will Deacon <will@...nel.org>; Mark
> Rutland <mark.rutland@....com>; kernel@...gutronix.de; Michael Riesch
> <michael.riesch@...fvision.net>; Robin Murphy <robin.murphy@....com>;
> Vincent Legoll <vincent.legoll@...il.com>; Rob Herring
> <robh+dt@...nel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley <conor+dt@...nel.org>;
> devicetree@...r.kernel.org; Sebastian Reichel
> <sebastian.reichel@...labora.com>; Sascha Hauer <s.hauer@...gutronix.de>;
> Jonathan Cameron <Jonathan.Cameron@...wei.com>; Chanwoo Choi
> <cw00.choi@...sung.com>
> Subject: [PATCH v8 11/26] PM / devfreq: rockchip-dfi: Handle LPDDR2
> correctly
>
> According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be set
> for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while at it
> turn the if/else if/else into switch/case which makes it easier to read.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> Reviewed-by: Sebastian Reichel <sebastian.reichel@...labora.com>
> Acked-by: Chanwoo Choi <cw00.choi@...sung.com>
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 571d72d1abd1c..8ce0191552ef1 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct
> devfreq_event_dev *edev)
> DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> + switch (dfi->ddr_type) {
> + case ROCKCHIP_DDRTYPE_LPDDR2:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23,
> DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> + break;
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4,
> DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> + break;
> + default:
> + break;
> + }
>
> /* enable count, use software mode */
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN,
> DDRMON_CTRL_SOFTWARE_EN),
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
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