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Message-ID: <MA0P287MB033232F5C170767F51198EC4FED4A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM>
Date: Thu, 19 Oct 2023 20:02:16 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Inochi Amaoto <inochiama@...look.com>,
Chao Wei <chao.wei@...hgo.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: Jisheng Zhang <jszhang@...nel.org>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
On 2023/10/19 7:18, Inochi Amaoto wrote:
> Add common GPIO devices for the CV180x and CV181x soc.
>
> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
> Reviewed-by: Jisheng Zhang <jszhang@...nel.org>
LGTM.
Acked-by: Chen Wang <unicorn_wang@...look.com>
> ---
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 55d4bc84faa0..d415cc758def 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> /*
> * Copyright (C) 2023 Jisheng Zhang <jszhang@...nel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@...look.com>
> */
>
> #include <dt-bindings/interrupt-controller/irq.h>
> @@ -53,6 +54,78 @@ soc {
> dma-noncoherent;
> ranges;
>
> + gpio0: gpio@...0000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3020000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@...1000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3021000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio2: gpio@...2000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3022000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio3: gpio@...3000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3023000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> uart0: serial@...0000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04140000 0x100>;
> --
> 2.42.0
>
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