| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20231019135905.3658215-1-peterlin@andestech.com>
Date: Thu, 19 Oct 2023 21:59:05 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <conor@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <paul.walmsley@...ive.com>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <prabhakar.mahadev-lad.rj@...renesas.com>, <tim609@...estech.com>,
<dylan@...estech.com>, <locus84@...estech.com>,
<dminus@...estech.com>,
"Yu Chien Peter Lin" <peterlin@...estech.com>
Subject: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller
Add "andestech,cpu-intc" compatible string for Andes INTC which
provides Andes-specific IRQ chip functions.
Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
---
Changes v1 -> v2:
- New patch
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..5b216e11c69f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -99,7 +99,9 @@ properties:
const: 1
compatible:
- const: riscv,cpu-intc
+ enum:
+ - riscv,cpu-intc
+ - andestech,cpu-intc
interrupt-controller: true
--
2.34.1
Powered by blists - more mailing lists