[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20231019140232.3660375-1-peterlin@andestech.com>
Date: Thu, 19 Oct 2023 22:02:32 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <geert+renesas@...der.be>, <magnus.damm@...il.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <paul.walmsley@...ive.com>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>,
<linux-renesas-soc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: <prabhakar.mahadev-lad.rj@...renesas.com>, <tim609@...estech.com>,
<dylan@...estech.com>, <locus84@...estech.com>,
<dminus@...estech.com>,
"Yu Chien Peter Lin" <peterlin@...estech.com>
Subject: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
Add "xandespmu" to ISA extensions, the SBI PMU driver will
probe the extension and use the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
---
Changes v1 -> v2:
- New patch
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a6345469e8c9..73c572056a04 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -26,7 +26,7 @@ cpu0: cpu@0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xandespmu";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
--
2.34.1
Powered by blists - more mailing lists