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Message-ID: <f620c7d4-6345-4ad0-8a45-c8089e3c34df@citrix.com>
Date: Sat, 21 Oct 2023 00:55:45 +0100
From: Andrew Cooper <andrew.cooper3@...rix.com>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>,
Peter Zijlstra <peterz@...radead.org>,
Josh Poimboeuf <jpoimboe@...nel.org>,
Andy Lutomirski <luto@...nel.org>,
Jonathan Corbet <corbet@....net>,
Sean Christopherson <seanjc@...gle.com>,
Paolo Bonzini <pbonzini@...hat.com>, tony.luck@...el.com,
ak@...ux.intel.com, tim.c.chen@...ux.intel.com
Cc: linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
kvm@...r.kernel.org,
Alyssa Milburn <alyssa.milburn@...ux.intel.com>,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
antonio.gomez.iglesias@...ux.intel.com,
Alyssa Milburn <alyssa.milburn@...el.com>
Subject: Re: [RESEND][PATCH 1/6] x86/bugs: Add asm helpers for executing VERW
On 20/10/2023 9:44 pm, Pawan Gupta wrote:
> +#define EXEC_VERW \
> + __EXEC_VERW(551f); \
> + /* nopl __KERNEL_DS(%rax) */ \
> + .byte 0x0f, 0x1f, 0x80, 0x00, 0x00; \
> +551: .word __KERNEL_DS; \
Is this actually wise from a perf point of view?
You're causing a data access to the instruction stream, and not only
that, the immediate next instruction. Some parts don't take kindly to
snoops hitting L1I.
A better option would be to simply have
.section .text.entry
.align CACHELINE
mds_verw_sel:
.word __KERNEL_DS
int3
.align CACHELINE
And then just have EXEC_VERW be
verw mds_verw_sel(%rip)
in the fastpaths. That keeps the memory operand in .text.entry it works
on Meltdown-vulnerable CPUs, but creates effectively a data cacheline
that isn't mixed into anywhere in the frontend, which also gets far
better locality of reference rather than having it duplicated in 9
different places.
Also it avoids playing games with hiding data inside an instruction.
It's a neat trick, but the neater trick is avoid it whenever possible.
~Andrew
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