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Message-ID: <SA1PR21MB13352433C4D72AE19F1FF56EBFDBA@SA1PR21MB1335.namprd21.prod.outlook.com>
Date: Fri, 20 Oct 2023 06:01:53 +0000
From: Dexuan Cui <decui@...rosoft.com>
To: Dave Hansen <dave.hansen@...el.com>,
KY Srinivasan <kys@...rosoft.com>,
Haiyang Zhang <haiyangz@...rosoft.com>,
"wei.liu@...nel.org" <wei.liu@...nel.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"x86@...nel.org" <x86@...nel.org>, "hpa@...or.com" <hpa@...or.com>,
"luto@...nel.org" <luto@...nel.org>,
"peterz@...radead.org" <peterz@...radead.org>,
"stefan.bader@...onical.com" <stefan.bader@...onical.com>,
Tim Gardner <tim.gardner@...onical.com>,
"roxana.nicolescu@...onical.com" <roxana.nicolescu@...onical.com>,
"cascardo@...onical.com" <cascardo@...onical.com>,
"Michael Kelley (LINUX)" <mikelley@...rosoft.com>,
"jgross@...e.com" <jgross@...e.com>,
"sathyanarayanan.kuppuswamy@...ux.intel.com"
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
"kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
"sashal@...nel.org" <sashal@...nel.org>,
"matija.glavinic-pecotic.ext@...ia.com"
<matija.glavinic-pecotic.ext@...ia.com>,
"linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] x86/mm: Print the encryption features correctly when a
paravisor is present
> From: Dave Hansen <dave.hansen@...el.com>
> Sent: Thursday, October 19, 2023 8:54 AM
> To: Dexuan Cui <decui@...rosoft.com>; KY Srinivasan
> [...]
> > --- a/arch/x86/hyperv/ivm.c
> > +++ b/arch/x86/hyperv/ivm.c
> > @@ -450,6 +450,16 @@ static bool hv_is_private_mmio(u64 addr)
> > return false;
> > }
> >
> > +static void hv_print_mem_enc_feature_info(void)
> > +{
> > + enum hv_isolation_type type = hv_get_isolation_type();
> > +
> > + if (type == HV_ISOLATION_TYPE_SNP)
> > + pr_info("Memory Encryption Features active: AMD
> SEV\n");
> > + else if (type == HV_ISOLATION_TYPE_TDX)
> > + pr_info("Memory Encryption Features active: Intel
> > TDX\n");
> > +}
>
> If we draw this to its logical conclusion, every paravisor will need a
> pr_info() for every hardware CoCo implementation. That M*N pr_info()s.
> That seems nuts.
This patch only modifies x86 related files. I think it's unlikely to see
a third hardware Coco implementation for x86 in the foreseeable feature (?)
When we have a third implementation, I suppose more code, e.g., the existing
print_mem_encrypt_feature_info(), will have to be changed as well.
Currently it looks like there is only 1 paravisor implementation.
I think we'll know if some code can be shared only when a second paravisor
implementation appears.
I can use the below version if you think it's better:
static const char *hv_mem_enc_features[] = {
[ HV_ISOLATION_TYPE_SNP ] = "AMD SEV",
[ HV_ISOLATION_TYPE_TDX ] = "Intel TDX",
};
static void hv_print_mem_enc_feature_info(void)
{
enum hv_isolation_type type = hv_get_isolation_type();
if (type < HV_ISOLATION_TYPE_SNP || type > HV_ISOLATION_TYPE_TDX)
return;
pr_info("Memory Encryption Features active:: %s\n",
hv_mem_enc_features[type]);
}
Thanks,
Dexuan
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